参数资料
型号: XRT75R12IB
厂商: Exar Corporation
文件页数: 62/90页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 12CH 420TBGA
标准包装: 40
类型: 线路接口装置(LIU)
驱动器/接收器数: 12/12
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 420-LBGA 裸露焊盘
供应商设备封装: 420-TBGA(35x35)
包装: 托盘
XRT75R12
62
REV. 1.0.4
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE 25: CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR224 (ADDRESS LOCATION = 0XE0)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
Channel 11
Interrupt
Enable
Channel 10
Interrupt
Enable
Channel 9
Interrupt
Enable
Channel 8
Interrupt
Enable
Channel 7
Interrupt
Enable
Channel 6
Interrupt
Enable
R/W
BIT
NUMBER
NAME
TYPE
DESCRIPTION
7,6
Reserved
5
4
3
2
1
0
Channel 11 Interrupt Enable
Channel 10 Interrupt Enable
Channel 9 Interrupt Enable
Channel 8 Interrupt Enable
Channel 7 Interrupt Enable
Channel 6 Interrupt Enable
R/W
Channel n Interrupt Enable Bit:
This READ/WRITE bit is used to:
To enable Channel n for Interrupt Generation at the Channel
Level
To disable all Interrupts associated with Channel n within the
XRT75R12
This is a "master" enable bit for each channel. This bit allows
control on a per channel basis to signal the Host of selected error
conditions.
If a bit is cleared, no interrupts from that channel will be sent to the
Host via the INT pin.
If the bit is set (logic 1), any generated interrupt in channel n that
has been enabled in the Interrupt Enable register (IERn) for the
channel will activate the INT pin to the Host.
0 - Disables all Channel n related Interrupts.
1 - Enables Channel n-related Interrupts. The user must enable
individual Channel n related Interrupts at the source level, before
they are can generate an interrupt.
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XRT75R12IB-L 功能描述:LIN 收发器 Attenuator RoHS:否 制造商:NXP Semiconductors 工作电源电压: 电源电流: 最大工作温度: 封装 / 箱体:SO-8
XRT75VL00 制造商:EXAR 制造商全称:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00_08 制造商:EXAR 制造商全称:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00D 制造商:EXAR 制造商全称:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER