参数资料
型号: XRT75R12IB
厂商: Exar Corporation
文件页数: 89/90页
文件大小: 0K
描述: IC LIU E3/DS3/STS-1 12CH 420TBGA
标准包装: 40
类型: 线路接口装置(LIU)
驱动器/接收器数: 12/12
规程: DS3,E3,STS-1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 420-LBGA 裸露焊盘
供应商设备封装: 420-TBGA(35x35)
包装: 托盘
XRT75R12
6
REV. 1.0.4
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
D25
AD25
G23
AA24
J24
U24
J3
U3
G4
AA3
D2
AD2
RLOS0
RLOS1
RLOS2
RLOS3
RLOS4
RLOS5
RLOS6
RLOS7
RLOS8
RLOS9
RLOS10
RLOS11
O
Receive Loss of Signal Output Indicator
This output pin indicates Loss of Signal (LOS) Defect condition for the corre-
sponding channel.
"Low" - Indicates that the corresponding Channel is NOT currently declaring the
LOS defect condition.
"High" - Indicates that the corresponding Channel is currently declaring the LOS
defect condition.
G22
AB26
K22
U22
L24
W25
L3
W2
K5
U5
G5
AB1
RLOL0
RLOL1
RLOL2
RLOL3
RLOL4
RLOL5
RLOL6
RLOL7
RLOL8
RLOL9
RLOL10
RLOL11
O
Receive Loss of Lock Output Indicator
This output pin indicates Loss of Lock (LOL) condition for the corresponding
channel.
"Low" - Indicates that the corresponding Channel is NOT declaring the LOL
condition.
"High" - Indicates that the corresponding Channel is currently declaring the LOL
condition.
NOTE: The Receive Section of a given channel will declare the LOL condition
anytime the frequency of the Recovered Clock (RCLK) signal differs
from that of the reference clock programmed for that channel by 0.5%
or more.
E25
AD26
G24
Y24
L22
T22
L5
T5
G3
Y3
E2
AD1
RxPOS0
RxPOS1
RxPOS2
RxPOS3
RxPOS4
RxPOS5
RxPOS6
RxPOS7
RxPOS8
RxPOS9
RxPOS10
RxPOS11
O
Receive Positive Data Output
The function of these output pins depends upon whether the channel has been
configured to operate in the Single-Rail or Dual-Rail Mode.
Dual-Rail Mode - Receive Positive Polarity Data Output
If the channel has been configured to operate in the Dual-Rail Mode, then all
positive-polarity data will be output via this pin. The negative-polarity data will
be output via the corresponding RxNEG_n pin. In other words, the Receive
Section of the corresponding Channel will pulse this output pin "High" for one
period of RCLK_n anytime it receives a positive-polarity pulse via the RTIP/
RRING input pins.
The data output via this pin is updated upon the active edge of RxCLK_n output
clock signal.
Single-Rail Mode - Receive Data Output
In the Single-Rail Mode, all Receive (or Recovered) data will be output via this
pin.
The data output via this pin is updated upon the active edge of RxCLK_n output
clock signal.
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