XRT94L31IB (Exar) PDF资料下载 Datasheet(99/133 页)

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参数资料

型号：	XRT94L31IB
厂商：	Exar Corporation
文件页数：	99/133页
文件大小：	0K
描述：	IC MAPPER DS3/E3/STS-1 504TBGA
标准包装：	24
应用：	网络切换
接口：	总线
电源电压：	3.14 V ~ 3.47 V
封装/外壳：	504-LBGA
供应商设备封装：	504-TBGA（35x35）
包装：	托盘
安装类型：	表面贴装

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XRT94L31

3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC

REV. 1.0.1

D15

E20

AE13

RxOHCLK_0

RxOHCLK_1

RxOHCLK_2

CMOS

Receive Overhead Data Output Interface - clock

This output pin functions as the Receive Overhead Clock output for the

receive system side interface when the XRT94L31 is configured to oper-

ate in DS3/E3 mode, however, it functions as the Receive STS-1 Over-

head Clock output when the device is configured to operate in the STS-1

mode.

When configured to operate in DS3/E3 mode:

The channel will output the overhead bits (within the incoming DS3 or E3

frames) via the RxOH_n output pin, upon the falling edge of this clock

signal.

As a consequence, the user's local terminal equipment should use the

rising edge of this clock signal to sample the data on both the RxOH and

RxOHFrame output pins.

NOTE: This clock signal is always active.

When configured to operate in STS-1 mode:

These output pins, along with RxOH_n, RxOHFrame_n, and

RxOHEnable_n function as the Receive STS-1 TOH and POH Output

Port.These output pins function as the Clock Output signals for the

Receive STS-1 TOH and POH Output Port. The RxOH_n,

RxSTS1Frame_n and RxOHEnable_n output pins are updated upon the

falling edge of this clock signal.

E15

D22

AD13

RxOHFRAME_0

RxOHFRAME_1

RxOHFRAME_2

CMOS

Receive Overhead Data Interface - Framing Pulse indicator

This output pin functions as the Receive Overhead Clock output for the

receive system side interface when the XRT94L31 is configured to oper-

ate in DS3/E3 mode, however, it functions as the Receive STS-1 Over-

head Clock output when the device is configured to operate in the STS-1

mode.

When configured to operate in DS3/E3 mode:

This output pin pulses "High" whenever the Receive Overhead Data

Output Interface block outputs the first overhead bit of a new DS3 or E3

frame.

When configured to operate in STS-1 mode:

These output pins, along with RxOH_n, RxOHEnable_n and RxOHClk_n

function as the Receive STS-1 TOH and POH Output Port.

These output pins will pulse "High" coincident with either of the following

events.

When the very first TOH byte (A1), of a given STS-1 frame, is being out-

put via the corresponding RxOH_n output pin.

When the very first POH byte (J1), of a given STS-1 frame, is being out-

put via the corresponding RxOH_n output pin.

The external circuitry can determine whether or not these output pins are

pulsing "High" for the first TOH or POH byte by checking the state of the

corresponding RxOHEnable_n output pin.

Y26

RxPERR

CMOS