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参数资料
| 型号： | ZL2105EVK2 |
| 厂商： | Intersil |
| 文件页数： | 18/36页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2 ZL2105 |
| 标准包装： | 1 |
| 系列： | * |
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ZL2105
Logic
high
SYNC
SYNC
200kHz – 2MHz
N/C
ZL2105
A) SYNC = output
Logic
200kHz – 2MHz
N/C
ZL2105
B) SYNC = input
N/C
high
SYNC
Open
SYNC
SYNC
200kHz – 2MHz
ZL2105
OR
Logic
ZL2105
OR
R SYNC
ZL2105
low
C) SYNC = Auto Detect
Figure 15. SYNC Pin Configurations.
Configuration C: SYNC AUTO DETECT
Table 13. Switching Frequency Selection
When the SYNC pin is configured in auto detect mode
(CFG pin is left OPEN), the device will automatically
check for a clock signal on the SYNC pin after enable
is asserted.
- If a valid clock signal is present, the ZL2105’s
SYNC Pin
LOW
OPEN
HIGH
Resistor
Frequency
200 kHz
400 kHz
1 MHz
oscillator will then synchronize both frequency and
phase with the rising edge of the external clock signal.
The incoming clock signal must be in the range of 200
kHz to 2 MHz with a minimum duty cycle, and must
be stable when the EN pin is asserted. See Table 3 for a
complete list of performance requirements for the
incoming clock signal.
- If no incoming clock signal is present, the ZL2105
will configure the switching frequency according to the
state of the SYNC pin as listed in Table 13. In this
configuration, the SYNC pin is sampled only on start-
up and will not modify its switching frequency if the
SYNC pin is re-configured after start-up (unless the
power is recycled).
18
If the user wishes to run the ZL2105 at a frequency not
listed in Table 13, the switching frequency can be set
using an external resistor, R SYNC , connected between
FN6851.2
March 30, 2011
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