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参数资料
| 型号： | ZL2105EVK2 |
| 厂商： | Intersil |
| 文件页数： | 7/36页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2 ZL2105 |
| 标准包装： | 1 |
| 系列： | * |
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ZL2105
Table 4. Pin Descriptions (continued)
Pin
Label
Type
1
Description
20,21
22,23
24,25
26
PGND
SW
VDDP
BST
PWR
I/O
PWR
PWR
Power ground. Common return for internal switching MOSFETs.
Switching node (level-shift common).
Bias power for internal switching MOSFETs (return is PGND).
Bootstrap V DD for level-shift driver (referenced to SW).
Regulated bias from internal 5V low-dropout regulator (return is PGND). Decouple
27
VR
PWR
with a 4.7 μF capacitor to PGND.
Connect 91? resistor between VR and VRA.
Regulated 5 V bias for internal analog circuitry (return is SGND).
28
VRA
PWR
Decouple with a 4.7 μF capacitor to SGND.
Connect 91? resistor between VR and VRA.
29
30
31
32
33
34
35
36
ePad
VDDL
VDDS
V25
FC
MGN
CFG
EN
PG
SGND
PWR
PWR
PWR
I
I
I
I
O
PWR
Internal logic supply. Connect to VRA or apply a 3.0-5.5 V external supply. Return is
SGND.
IC supply voltage (return is SGND).
Regulated bias from internal 2.5 V low-dropout regulator. Decouple with a 10μF
capacitor.
Frequency compensation select pin. Used to set loop compensation.
Signal that enables margining of output voltage.
Configuration pin. Sets switching phase delay and sequencing order.
Enable input. Active high signal enables the device.
Power good output. This pin transitions high 100 ms after output voltage stabilizes
within regulation band. Programmable open drain output. Factory default is open drain.
Exposed thermal pad. Common return for analog signals; internal connection to
SGND. Connect to low impedance ground plane.
Notes:
1.
I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins. Please refer to Section 4.4 “ Multi-mode Pins, ” on
page 12.
7
FN6851.2
March 30, 2011
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