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| 型号： | ZL2105EVK2 |
| 厂商： | Intersil |
| 文件页数： | 6/36页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2 ZL2105 |
| 标准包装： | 1 |
| 系列： | * |
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ZL2105
2. Pin Descriptions
DGND
SYNC
SA
UVLO
1
2
3
4
27
26
25
24
VR
BST
VDDP
VDDP
ILIM
SCL
SDA
SALRT
XTEMP
5
6
7
8
9
ZL2105
Exposed Paddle
Connect to SGND
23
22
21
20
19
SW
SW
PGND
PGND
CP2
Figure 2. ZL2105 Pin Configurations (top view)
Table 4. Pin Descriptions
Pin
Label
Type
1
Description
1
DGND
PWR
Digital ground. Common return for digital signals. Connect to low impedance ground
plane.
Clock synchronization input. Used to set switching frequency of internal clock or for
2
SYNC
I/O, M
synchronization to external frequency reference. Programmable open drain output.
Factory default is push-pull
3
4
5
6
7
8
9
10,11
12
13
14
15
16
17
18, 19
SA
UVLO
ILIM
SCL
SDA
SALRT
XTEMP
V0, V1
DLY
SS
VTRK
VSEN
NC
VDR
CP1,CP2
I,M
I,M
I,M
I/O
I/O
O
I
I,M
I,M
I,M
I
I
-
PWR
I/O
Serial address pin used to assign unique SMBus address to each IC.
Sets the input undervoltage lockout threshold that disables the device.
Sets the current limit threshold level.
Serial clock signal for system communications.
Serial data signal for system communications.
SMBus alert signal.
External temperature sensor input.
Output voltage select pins. Used to set the output voltage.
Soft start delay select pin. Sets the delay from when EN is asserted until the output
voltage starts to ramp.
Digital soft-start/stop. Sets the ramp period for the output to reach the desired regulation
point (after soft-start delay period, if applicable).
Track input. Allows the output to track another voltage.
Output voltage positive feedback sensing node.
No internal connection.
Supply pin for internal drivers.
Level-shift charge pump for 5 V operation. Connect external capacitor.
Notes:
1.
I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins.
6
FN6851.2
March 30, 2011
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