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参数资料
| 型号： | ZL2105EVK2 |
| 厂商： | Intersil |
| 文件页数： | 4/36页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD 2 ZL2105 |
| 标准包装： | 1 |
| 系列： | * |
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ZL2105
Table 3. Electrical Specifications
V DDP = V DDS = 12 V, T A = -40 C to 85 C unless otherwise noted. Typical values are at T A = 25 C.
Parameter
Conditions
Min
(Note 3)
Typ
Max
(Note 3)
Unit
Input and Supply Characteristics
I DDS supply current
I DDL supply current
I DDS shutdown current
I DDL shutdown current
VR reference output voltage
VRA reference output voltage
V25 reference output voltage
f SW = 200 kHz, no load
f SW = 1 MHz, no load
f SW = 200 kHz, no load
f SW = 1 MHz, no load
EN = 0 V, VDDL tied to VRA,
No I 2 C/SMBus activity
EN = 0 V, VDDL = 5 V,
No I 2 C/SMBus activity
V DD > 5.5 V, I VR < 5 mA
V DD > 5.5 V, I VRA < 35 mA
I V25 < 50 mA
–
–
–
–
–
–
4.5
4.5
2.25
2
5
8
10
0.7
225
5.2
5.2
2.5
3
6
16
20
2
500
5.5
5.5
2.75
mA
mA
mA
mA
mA
μA
V
V
V
Output Characteristics
Output Current
–
–
3
A
Output voltage adjustment range 1
Output voltage setpoint resolution
VSEN output voltage accuracy
VSEN input bias current
Soft start delay duration range 2
Soft start delay duration accuracy
Soft start ramp duration range
Soft start ramp duration accuracy
V IN > V OUT
Set using resistors
Set using I 2 C/SMBus
Includes line, load, temp
VSEN = 5.5 V
Set using DLY pin or resistor
Set using I 2 C/SMBus
Set using SS pin
Set using resistor or via I 2 C
0.6
–
–
-1
–
7
0.007
–
10
0
–
–
10
±0.025
–
100
–
–
6
–
–
100
5.0
–
–
1
200
200
500
–
100
200
–
V
mV
% FS
%
μA
ms
s
ms
ms
ms
μs
Logic Input/Output Characteristics
Logic input current
EN, SCL, SDA pins
-250
250
nA
Logic input low, V IL
–
–
0.8
V
Logic input OPEN (N/C)
Logic input high, V IH
Logic output low, V OL
Logic output high, V OH
Multi-mode logic pins
I OL ≤ 4 mA
I OH ≥ -2 mA
–
2.0
–
2.25
1.4
–
–
–
–
–
0.4
–
V
V
V
V
Tracking
VTRK input bias current
VTRK tracking accuracy
VTRK = 5.5 V
100% Tracking, V OUT - VTRK
–
- 100
110
–
200
+ 100
μA
mV
Notes:
1. Does not include margin
2. The device requires approximately 6 ms following an enable signal and prior to output ramp. The minimum
settable delay is 7 ms.
3. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Table 3 is continued on the following page
4
FN6851.2
March 30, 2011
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