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参数资料
| 型号： | 42S16400A |
| 厂商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 1梅格位× 16位× 4银行（64兆位）同步动态RAM |
| 文件页数： | 10/55页 |
| 文件大小： | 472K |
| 代理商： | 42S16400A |
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IS42S16400A
ISSI
18
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.C
04/16/03
DON'T CARE
UNDEFINED
CLK
COMMAND
DQ
READ
NOP
CAS Latency - 3
tAC
tOH
DOUT
T0
T1
T2
T3
T4
tLZ
CLK
COMMAND
DQ
READ
NOP
CAS Latency - 2
tAC
tOH
DOUT
T0
T1
T2
T3
tLZ
CAS Latency
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
piece of output data. The latency can be set to two or three clocks.
If a READ command is registered at clock edge n, and the
latency is
m clocks, the data will be available by clock
edge
n + m. The DQs will start driving as a result of the
clock edge one cycle earlier
(n + m - 1), and provided that
the relevant access times are met, the data will be valid
by clock edge
n + m. For example, assuming that the
clock cycle time is such that all relevant access times are
met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as shown
in CAS Latency diagrams. The Allowable Operating
Frequency table indicates the operating frequencies at
which each CAS latency setting can be used.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
Operating Mode
The normal operating mode is selected by setting M7 and M8
to zero; the other combinations of values for M7 and M8 are
CAS Latency
Allowable Operating Frequency (MHz)
Speed
CAS Latency = 2
CAS Latency = 3
6
100
166
7
100
133
10
100
—
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1, the
programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
相关PDF资料 |
PDF描述 |
|---|---|
| 42S16800A | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 42S32200 | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 4300-000 | EMI/RFI FILTER Hermetically Sealed |
| 4300-000LF | |
| 4300-001 | EMI/RFI FILTER Hermetically Sealed |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 42S16400B-6TLTR | 制造商:Integrated Silicon Solution Inc 功能描述: |
| 42S16800A | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 42S16800L | 制造商:NEC 制造商全称:NEC 功能描述:3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE |
| 42S16800L-A60 | 制造商:NEC 制造商全称:NEC 功能描述:3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE |
| 42S16800L-A70 | 制造商:NEC 制造商全称:NEC 功能描述:3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE |
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