参数资料
型号: 42S16400A
厂商: Integrated Silicon Solution, Inc.
英文描述: 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述: 1梅格位× 16位× 4银行(64兆位)同步动态RAM
文件页数: 27/55页
文件大小: 472K
代理商: 42S16400A
IS42S16400A
ISSI
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
33
Rev.C
04/16/03
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
DOUT a
DOUT a+1
DOUT b
DOUT b+1
BANK n,
COL a
BANK m,
COL b
CAS Latency - 3 (BANK n)
CAS Latency - 3 (BANK m)
tRP - BANK n
tRP -BANKm
READ - AP
BANK n
READ - AP
BANK m
Page Active
READ with Burst of 4
Interrupt Burst, Precharge
Idle
Page Active
READ with Burst of 4
Precharge
Internal States
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQM
DQ
T0
T1
T2
T3
T4
T5
T6
T7
NOP
DOUT a
DIN b
DIN b+1
DIN b+2
DIN b+3
BANK n,
COL a
BANK m,
COL b
CAS Latency - 3 (BANK n)
tRP - BANK n
tRP -BANKm
WRITE - AP
BANK n
WRITE - AP
BANK m
READ with Burst of 4
Interrupt Burst, Precharge
Idle
Page Active
WRITE with Burst of 4
Write-Back
Internal States
Page Active
BURST READ/SINGLE WRITE
The burst read/single write mode is entered by programming
the write burst mode bit (M9) in the mode register to a logic 1.
In this mode, all WRITE commands result in the access of a
single column location (burst of one), regardless of the
programmed burst length. READ commands access
columns according to the programmed burst length and
sequence, just as in the normal mode of operation (M9 = 0).
CONCURRENT AUTO PRECHARGE
An access command (READ or WRITE) to another bank
while an access command with auto precharge enabled is
executing is not allowed by SDRAMs, unless the SDRAM
supports CONCURRENT AUTO PRECHARGE. ISSI
SDRAMs support CONCURRENT AUTO PRECHARGE.
Four cases where CONCURRENT AUTO PRECHARGE
occurs are defined below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a READ on bank n, CAS
latency later. The PRECHARGE to bank n will begin
when the READ to bank m is registered.
2. Interrupted by a WRITE (with or without auto precharge):
A WRITE to bank m will interrupt a READ on bank n
when registered. DQM should be used two clocks prior
to the WRITE command to prevent bus contention. The
PRECHARGE to bank n will begin when the WRITE to
bank m is registered.
Fig CAP 1 - READ With Auto Precharge interrupted by a READ
Fig CAP 2 - READ With Auto Precharge interrupted by a WRITE
相关PDF资料
PDF描述
42S16800A 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM
42S32200 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM
4300-000 EMI/RFI FILTER Hermetically Sealed
4300-000LF
4300-001 EMI/RFI FILTER Hermetically Sealed
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