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参数资料
| 型号： | 42S16400A |
| 厂商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 1梅格位× 16位× 4银行（64兆位）同步动态RAM |
| 文件页数： | 23/55页 |
| 文件大小： | 472K |
| 代理商： | 42S16400A |
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IS42S16400A
ISSI
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
3
Rev.C
04/16/03
PIN FUNCTIONS
Symbol
Pin No.
Type
Function (In Detail)
A0-A11
23 to 26
Input Pin
Address Inputs: A0-A11 are sampled during the ACTIVE
29 to 34
command (row-address A0-A11) and READ/WRITE command (A0-A7
22, 35
with A10 defining auto precharge) to select one location out of the memory array
in the respective bank. A10 is sampled during a PRECHARGE command to
determine if all banks are to be precharged (A10 HIGH) or bank selected by
BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
MODE REGISTER command.
BA0, BA1
20, 21
Input Pin
Bank Select Address: BA0 and BA1 defines which bank the ACTIVE, READ,
WRITE or PRECHARGE command is being applied.
CAS
17
Input Pin
CAS, in conjunction with the RAS and WE, forms the device command. See the
"Command Truth Table" for details on device commands.
CKE
37
Input Pin
The CKE input determines whether the CLK input is enabled. The next rising edge
of the CLK signal will be valid when is CKE HIGH and invalid when LOW. When
CKE is LOW, the device will be in either power-down mode, clock suspend mode,
or self refresh mode. CKE is an asynchronous input.
CLK
38
Input Pin
CLK is the master clock input for this device. Except for CKE, all inputs to this
device are acquired in synchronization with the rising edge of this pin.
CS
19
Input Pin
The
CS input determines whether command input is enabled within the device.
Command input is enabled when
CS is LOW, and disabled with CS is HIGH. The
device remains in the previous state when
CS is HIGH.
I/O0 to
2, 4, 5, 7, 8, 10,
I/O Pin
I/O0 to I/O15 are I/O pins. I/O through these pins can be controlled in byte units
I/O15
11,13, 42, 44, 45,
using the LDQM and UDQM pins.
47, 48, 50, 51, 53
LDQM,
15, 39
Input Pin
LDQM and UDQM control the lower and upper bytes of the I/O buffers. In read
UDQM
mode, LDQM and UDQM control the output buffer. When LDQM or UDQM is
LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The
outputs go to the HIGH impedance state when LDQM/UDQM is HIGH. This
function corresponds to
OE in conventional DRAMs. In write mode, LDQM and
UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding
buffer byte is enabled, and data can be written to the device. When LDQM or
UDQM is HIGH, input data is masked and cannot be written to the device.
RAS
18
Input Pin
RAS, in conjunction with CAS and WE, forms the device command. See the
"Command Truth Table" item for details on device commands.
WE
16
Input Pin
WE, in conjunction with RAS and CAS, forms the device command. See the
"Command Truth Table" item for details on device commands.
VCCQ
3, 9, 43, 49
Power Supply Pin
VCCQ is the output buffer power supply.
VCC
1, 14, 27
Power Supply Pin
VCC is the device internal power supply.
GNDQ
6, 12, 46, 52
Power Supply Pin
GNDQ is the output buffer ground.
GND
28, 41, 54
Power Supply Pin
GND is the device internal ground.
相关PDF资料 |
PDF描述 |
|---|---|
| 42S16800A | 16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 42S32200 | 512K Bits x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 4300-000 | EMI/RFI FILTER Hermetically Sealed |
| 4300-000LF | |
| 4300-001 | EMI/RFI FILTER Hermetically Sealed |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 42S16400B-6TLTR | 制造商:Integrated Silicon Solution Inc 功能描述: |
| 42S16800A | 制造商:ISSI 制造商全称:Integrated Silicon Solution, Inc 功能描述:16Meg x 8, 8Meg x16 & 4Meg x 32 128-MBIT SYNCHRONOUS DRAM |
| 42S16800L | 制造商:NEC 制造商全称:NEC 功能描述:3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE |
| 42S16800L-A60 | 制造商:NEC 制造商全称:NEC 功能描述:3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE |
| 42S16800L-A70 | 制造商:NEC 制造商全称:NEC 功能描述:3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, FAST PAGE MODE |
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