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| 型号： | 71M6511-IGTR/F |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
| 封装： | LEAD FREE, LQFP-64 |
| 文件页数： | 19/98页 |
| 文件大小： | 1278K |
| 代理商： | 71M6511-IGTR/F |
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71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
NOVEMBER 2010
Page: 26 of 98
2005–2010 Teridian Semiconductor Corporation
V2.7
A Maxim Integrated Products Brand
Bit
Symbol
Function
TCON.7
TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows. This flag
can be cleared by software and is automatically cleared when an interrupt is
processed.
TCON.6
TR1
Timer 1 Run control bit. If cleared, Timer 1 stops.
TCON.5
TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can be
cleared by software and is automatically cleared when an interrupt is
processed.
TCON.4
TR0
Timer 0 Run control bit. If cleared, Timer 0 stops.
TCON.3
IE1
Interrupt 1 edge flag is set by hardware when the falling edge on external pin
int1 is observed. Cleared when an interrupt is processed.
TCON.2
IT1
Interrupt 1 type control bit. Selects either the falling edge or low level on input
pin to cause an interrupt.
TCON.1
IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external pin
int0 is observed. Cleared when an interrupt is processed.
TCON.0
IT0
Interrupt 0 type control bit. Selects either the falling edge or low level on input
pin to cause interrupt.
Table 23: The TCON Register Bit Functions
Table 24 specifies the combinations of operation modes allowed for timer 0 and timer 1:
Timer 1
Mode 0
Mode 1
Mode 2
Timer 0 - mode 0
YES
Timer 0 - mode 1
YES
Timer 0 - mode 2
Not allowed
YES
Table 24: Timer Modes
Timer/Counter Mode Control Register (PCON):
MSB
LSB
SMOD
Table 25: The PCON Register
The SMOD bit in the PCON register doubles the baud rate when set.
WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the
watchdog timer is disabled and all registers are set to zero. The watchdog consists of a 16-bit counter (WDT), a reload register
(WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be stopped unless the
internal reset signal becomes active.
Note: It is recommended to use the hardware watchdog timer instead of the software watchdog timer.
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register enters the state 0x7CFF,
an asynchronous WDTS signal will become active. The signal WDTS sets bit 6 in the IP0 register and requests a reset state.
WDTS is cleared either by the reset signal or by changing the state of the WDT timer.
相关PDF资料 |
PDF描述 |
|---|---|
| 71M6511-IGT/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
| 71M6511-IGT | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
| 71M6511-IGTR | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
| 71M6511H-IGTR/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
| 71M6511H-IGT/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
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