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参数资料
| 型号： | 71M6511-IGTR/F |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
| 封装： | LEAD FREE, LQFP-64 |
| 文件页数： | 58/98页 |
| 文件大小： | 1278K |
| 代理商： | 71M6511-IGTR/F |
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71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
NOVEMBER 2010
Page: 61 of 98
2005–2010 Teridian Semiconductor Corporation
V2.7
A Maxim Integrated Products Brand
FLSH_ERASE
SFR 94
W
Flash Erase Initiate
FLSH_ERASE is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle.
(default = 0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write
to FLSH_PGADR @ SFR 0xB7.
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a write
to FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must
be enabled.
Any other pattern written to FLSH_ERASE will have no effect.
FLSH_MEEN
SFR B2[1]
W
Mass Erase Enable
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
FLSH_PGADR
SFR B7[7:1]
W
Flash Page Erase Address
FLSH_PGADR[6:0] – Flash Page Address (page 0 thru 127) that will be
erased during the Page Erase cycle. (default = 0x00).
Must be re-written for each new Page Erase cycle.
FLSH_PWE
SFR B2[0]
R/W
Program Write Enable
0 – MOVX commands refer to XRAM Space, normal operation
(default).
1 – MOVX @DPTR,A moves A to Program Space (flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to
this bit are inhibited when interrupts are enabled.
IE_XFER
IE_RTC
SFR E8[0]
SFR E8[1]
R/W
Interrupt flags. These flags are part of the WDI SFR register and mo-
nitor the XFER_BUSY interrupt and the RTC_1SEC interrupt. The
flags are set by hardware and must be cleared by the interrupt handler.
See also WD_RST.
INTBITS
SFR F8[6:0]
R
Interrupt inputs. The MPU may read these bits to see the input to
external interrupts INT0, INT1, up to INT6. These bits do not have any
memory and are primarily intended for debug use.
LCD_BSTEN
2020[7]
R/W
Enables the LCD voltage boost circuit.
LCD_CLK[1:0]
2021[1:0]
R/W
Sets the LCD clock frequency for COM/SEG pins (not the frame rate.
Note: fw = CKFIR/128
00: fw/2
9, 01: f
w/2
8, 10: f
w/2
7, 11: f
w/2
6
LCD_EN
2021[5]
R/W
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
ground as are the COM and SEG outputs.
LCD_FS[4:0]
2022[4:0]
R/W
Controls the LCD full scale voltage, VLC2:
)
31
_
3
.
0
7
.
0
(
2
FS
LCD
VLCD
VLC
+
=
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| 71M6511-IGT/F | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
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| 71M6511-IGTR | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64 |
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