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参数资料
| 型号： | 71M6542G-IGT/F |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封装： | LEAD FREE, LQFP-100 |
| 文件页数： | 114/165页 |
| 文件大小： | 2208K |
| 代理商： | 71M6542G-IGT/F |
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52
2008–2011 Teridian Semiconductor Corporation
v1.1
Table 42: RTC Control Registers
Name
Location
Rst
Wk
Dir
Description
RTC_ADJ[6:0]
2504[6:0]
00
–
R/W
Register for analog RTC frequency adjustment.
RTC_P[16:14]
RTC_P[13:6]
RTC_P[5:0]
289B[2:0]
289C[7:0]
289D[7:2]
4
0
4
0
R/W
Registers for digital RTC adjustment.
0x0FFBF
≤ RTC_P ≤ 0x10040
RTC_Q[1:0]
289D[1:0]
0
R/W
Register for digital RTC adjustment.
RTC_RD
2890[6]
0
R/W
Freezes the RTC shadow register so it is suitable for
MPU reads. When RTC_RD is read, it returns the
status of the shadow register: 0 = up to date, 1 = frozen.
RTC_WR
2890[7]
0
R/W
Freezes the RTC shadow register so it is suitable for
MPU write operations. When RTC_WR is cleared,
the contents of the shadow register written to the RTC
counter on the next RTC clock (~500 Hz). When
RTC_WR is read, it returns 1 as long as RTC_WR is
set. It continues to return one until the RTC counter is
updated.
RTC_FAIL
2890[4]
0
R/W
Indicates that a count error has occurred in the RTC
and that the time is not trustworthy. This bit can be
cleared by writing a 0.
RTC_SBSC[7:0]
2892[7:0]
R
Time remaining since the last 1 second boundary.
LSB = 1/128 second.
2.5.4.3 RTC Rate Control
Two rate adjustment mechanisms are available:
The first rate adjustment mechanism is an analog rate adjustment, using the I/O RAM register
RTCA_ADJ[6:0] (I/O RAM 0x2504[6:0]), that trims the crystal load capacitance.
The second rate adjustment mechanism is a digital rate adjust that affects the way the clock frequency
is processed in the RTC.
Setting RTCA_ADJ[6:0] to 00 minimizes the load capacitance, maximizing the oscillator frequency. Setting
RTCA_ADJ[6:0] to 7F maximizes the load capacitance, minimizing the oscillator frequency. The adjustable
capacitance is approximately:
pF
ADJ
RTCA
C
ADJ
5
.
16
128
_
=
The precise amount of adjustment depends on the crystal properties, the PCB layout and the value of the
external crystal capacitors. The adjustment may occur at any time, and the resulting clock frequency should
be measured over a one-second interval.
The second rate adjustment is digital, and can be used to adjust the clock rate up to
±988ppm, with a
resolution of 3.8 ppm (±1.9 ppm). Note that 3.8 ppm corresponds to 1-LSB of the 19-bit quantity formed
by 4*RTCP+RTCQ and 1.9 ppm corresponds to -LSB. The rate adjustment is implemented starting at
the next second-boundary following the adjustment. Since the LSB results in an adjustment every four
seconds, the frequency should be measured over an interval that is a multiple of four seconds.
The clock rate is adjusted by writing the appropriate values to RTC_P[16:0] (I/O RAM 0x289B[2:0], 0x289C,
0x289D[7:2]) and RTC_Q[1:0] (I/O RAM 0x289D[1:0]). Updates to RTC rate adjust registers, RTC_P and
RTC_Q, are done through the shadow register described above. The new values are loaded into the
counters when RTC_WR (I/O RAM 0x2890[7]) is lowered.
The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency by
ppm,
RTC_P and RTC_Q are calculated using the following equation:
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