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参数资料
| 型号： | 71M6542G-IGT/F |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封装： | LEAD FREE, LQFP-100 |
| 文件页数： | 141/165页 |
| 文件大小： | 2208K |
| 代理商： | 71M6542G-IGT/F |
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v1.1
2008–2011 Teridian Semiconductor Corporation
77
SPI Flash Mode (SFM)
In normal operation, the SPI slave interface cannot read or write the flash memory. However, the
71M6541D/F and 71M6542F support an SPI Flash Mode (SFM) which facilitates initial programming of
the flash memory. When in SFM mode, the SPI can erase, read, and write the flash memory. Other
memory elements such as XRAM and I/O RAM are not accessible in this mode. In order to protect the
flash contents, several operations are required before the SFM mode is successfully invoked.
In SFM mode, n byte reads and dual-byte writes to flash memory are supported. See the SPI Transactions
description on Page 73 for the format of read and write commands. Since the flash write operation is always
based on a two-byte word, the initial address must always be even. Data is written to the 16-bit flash
memory bus after the odd word is written.
In SFM mode, the MPU is completely halted. For this reason, the interrupt feature described in the SPI
Transaction section above is not available in SFM mode. The 71M6541D/F and 71M6542F must be reset
by the WD timer or by the RESET pin in order to exit SFM mode.
Invoking SFM
The following conditions must be met prior to invoking SFM:
Pin ICE_E = 1. This disables the watchdog and adds another layer of protection against inadvertent
Flash corruption.
The external power source (V3P3SYS, V3P3A) is at the proper level (> 3.0 VDC).
PREBOOT = 0 (SFR 0xB2[7]). This validates the state of the SECURE bit (SFR 0xB2[6]).
SECURE = 0. This I/O RAM register indicates that SPI secure mode is not enabled. Operations are
limited to SFM Mass Erase mode if the SECURE bit = 1 (Flash read back is not allowed in Secure mode).
FLSH_UNLOCK[3:0] (I/O RAM 0x2702[7:4]) = 0010.
The I/O RAM registers SFMM (I/O RAM 0x2080) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only
the SPI interface has access to these two registers. This eliminates an indirect path from the MPU for
disabling the watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This
sequential write process prevents inadvertent entering of SFM.
The sequence for invoking SFM is:
First, write to the SFMM (I/O RAM 0x2080) register. The value written to this register defines the SFM
mode.
o
0xD1: Mass Erase mode. A Flash Mass erase cycle is invoked upon entering SFM.
o
0x2E: Flash Read back mode. SFM is entered for Flash read back purposes. Flash writes
are not be blocked and it is up to the user to guarantee that only previously unwritten
locations are written. This mode is not accessible when SPI secure mode is set.
o
SFM is not invoked if any other pattern is written to the SFMM register.
Next, write 0x96 to the SFMS (I/O RAM 0x2081) register. This action invokes SFM provided that the
previous write operation to SFMM met the requirements. Writing any other pattern to this register does
not invoke SFM. Additionally, any write operations to this register automatically reset the previously
written SFMM register values to zero.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 71M6542G-IGTR/F | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
| 71M6542GT-IGT/F | 制造商:Maxim Integrated Products 功能描述:1-PHASE, 128KB, PRES TEMP SENSOR - Bulk |
| 71M6542GT-IGTR/F | 制造商:Maxim Integrated Products 功能描述:1-PHASE, 128KB, PRES TEMP SENSOR - Tape and Reel |
| 71M6543F | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Selectable Gain of 1 or 8 for One Current Energy Meter ICs Metrology Compensation |
| 71M6543F-DB | 功能描述:开发板和工具包 - 8051 71M6543 Eval Kit RoHS:否 制造商:Silicon Labs 产品:Development Kits 工具用于评估:C8051F960, Si7005 核心: 接口类型:USB 工作电源电压: |
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