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参数资料
| 型号： | 71M6542G-IGT/F |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封装： | LEAD FREE, LQFP-100 |
| 文件页数： | 138/165页 |
| 文件大小： | 2208K |
| 代理商： | 71M6542G-IGT/F |
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74
2008–2011 Teridian Semiconductor Corporation
v1.1
When SPI_CSZ rises, SPI command bytes that are not of the form x000 0000 update the SPI_CMD (SFR
0xFD) register and then cause an interrupt to be issued to the MPU. The exception is if the transaction was
a single byte. In this case, the SPI_CMD byte is always updated and the interrupt issued. SPI_CMD is not
cleared when SPI_CSZ is high.
The SPI port supports data transfers up to 10 Mb/s. A serial read or write operation requires at least 8
clocks per byte, guaranteeing SPI access to the RAM is no faster than 1.25 MHz, thus ensuring that SPI
access to DRAM is always possible.
Table 62: SPI Transaction Fields
Field
Name
Required
Size
(bytes)
Description
Address
Yes, except for
single-byte
transaction
2
16-bit address. The address field is not required if the
transaction is a simple SPI command.
Command
Yes
1
8-bit command. This byte can be used as a command to the
MPU. In multi-byte transactions, the MSB is the R/W bit.
Unless the transaction is multi-byte and SPI_CMD is exactly
0x80 or 0x00, the SPI_CMD register is updated and an SPI
interrupt is issued. Otherwise, the SPI_CMD register is
unchanged and the interrupt is not issued.
Status
Yes, if transaction
includes DATA
1
8-bit status field, indicating the status of the previous
transaction. This byte is also available in the MPU memory
map as SPI_STAT (I/O RAM 0x2708) register. See Table 64
for the contents.
Data
Yes, if transaction
includes DATA
1 or
more
The read or write data. Address is auto incremented for
each new byte.
The SPI_STAT byte is output on every SPI transaction and indicates the parity of the previous transaction
and the error status of the previous transaction. Potential error sources are:
71M654x not ready.
Transaction not ending on a byte boundary.
SPI Safe Mode
Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus
disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI
SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte transfer
region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use the
SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the
SPI_SAFE bit (I/O RAM 0x270C[3]).
Single-Byte Transaction
If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value, single-
byte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated.
Multi-Byte Transaction
As shown in Figure 27, multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte,
and a sequence of data bytes. A multi byte transaction is three or more bytes.
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