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参数资料
型号： 71M6542G-IGT/F
厂商： MAXIM INTEGRATED PRODUCTS INC
元件分类： 模拟信号调理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封装： LEAD FREE, LQFP-100
文件页数： 134/165页
文件大小： 2208K
代理商： 71M6542G-IGT/F
70
2008–2011 Teridian Semiconductor Corporation
v1.1
LCD Drivers (71M6542F)
With a maximum of 56 LCD driver pins available, the 71M6542D/F is capable of driving up to 6 x 56 = 336
pixels of an LCD display when using the 6 x multiplex mode. At eight pixels per digit, this corresponds to
42 digits.
LCD segment data is written to the LCD_SEGn[5:0] I/O RAM registers as described in 2.5.8.3 Digital I/O
for the 71M6542F.
SEG46 through SEG50 cannot be configured as DIO pins. Display data for these pins are written to I/O
RAM fields LCD_SEG46[5:0] (I/O RAM 0x243E[5:0]) through LCD_SEG50[5:0] (I/O RAM 0x2442[5:0]); see
Table 59. The associated pins function as ICE interface pins, and the ICE functionality overrides the LCD
function whenever ICE_E is pulled high.
Table 59: 71M6542F LCD Data Registers for SEG46 to SEG50
SEG
46
47
48
49
50
Pin #
93
92
58
57
56
Configuration:
Always LCD pins, except
when used for ICE interface
or TMUXOUT/TMUX2OUT.
SEG Data Register
L
CD
_SE
G
D
IO
46[
5:0]
L
CD
_SE
G
D
IO
47[
5:0]
LC
D_
S
E
GDI
O4
8
[5
:0]
L
CD
_SE
G
D
IO
49[
5:0]
L
CD
_SE
G
D
IO
50[
5:0]
2.5.9
EEPROM Interface
The 71M6541D/F provides hardware support for either a two-pin or a three-wire (-wire) type of EEPROM
interface. The interfaces use the SFR EECTRL (SFR 0x9F) and EEDATA (SFR 0x9E) registers for
communication.
2.5.9.1 Two-pin EEPROM Interface
The dedicated 2-pin serial interface communicates with external EEPROM devices and is intended for
use with I
2C devices. The interface is multiplexed onto the SEGDIO2 (SDCK) and SEGDIO3 (SDATA)
pins and is selected by setting DIO_EEX[1:0] = 01 (I/O RAM 0x2456[7:6]). The MPU communicates with
the interface through the SFR registers EEDATA and EECTRL. If the MPU wishes to write a byte of data
to the EEPROM, it places the data in EEDATA and then writes the Transmit code to EECTRL. This
initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also asserted when
BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged the trans-
mission.
A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon
completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each
transmission, and then holds in a high state until the next transmission. The EECTRL bits when the
two-pin interface is selected are shown in Table 60.
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