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参数资料
| 型号： | 71M6542G-IGT/F |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封装： | LEAD FREE, LQFP-100 |
| 文件页数： | 76/165页 |
| 文件大小： | 2208K |
| 代理商： | 71M6542G-IGT/F |
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2008–2011 Teridian Semiconductor Corporation
v1.1
MUX_CTRL launches each pass of the CE through its code. Conceptually, MUX_CTRL is clocked by
CK32, the 32768 Hz clock from the PLL block. The behavior of the MUX_CTRL circuit is governed by:
CHOP_E[1:0] (I/O RAM 0x2106[3:2])
MUX_DIV[3:0] (I/O RAM 0x2100[7:4])
FIR_LEN[1:0] (I/O RAM 0x210C[2:1])
ADC_DIV (I/O RAM 0x2200[5])
The duration of each multiplexer state depends on the number of ADC samples processed by the FIR as
determined by the FIR_LEN[1:0] (I/O RAM 0x210C[2:1] control field. Each multiplexer state starts on the
rising edge of CK32, the 32-kHz clock.
It is recommended that MUX_DIV[3:0] (I/O RAM 0x2200[2:0]) be set to zero while changing the ADC
configuration. Although not required, it minimizes system transients that might be caused by momentary
shorts between the ADC inputs, especially when changing the DIFFn_E control bits (I/O RAM 0x210C[5:4]).
After the configuration bits are set, MUX_DIV[3:0] should be set to the required value.
Additionally, the ADC can be configured to operate at rate (32768*75=2.46MHz). In this mode, the
bias current to the ADC amplifiers is reduced and overall system power is reduced. The ADC_DIV (I/O
RAM 0x2200[5]) bit selects full speed or half speed. At half speed, if FIR_LEN[1:0] is set to 01 (288),
each conversion requires 4 XTAL cycles, resulting in a 2520Hz sample rate when MUX_DIV[3:0] = 3.
Note that in order to work with these power-reducing settings, a corresponding CE code is required.
The duration of each time slot in CK32 cycles depends on FIR_LEN[1:0], ADC_DIV and PLL_FAST:
Time_Slot_Duration (PLL_FAST = 1) = (FIR_LEN[1:0]+1) * (ADC_DIV+1)
Time_Slot_Duration (PLL_FAST = 0) = 3*(FIR_LEN[1:0]+1) * (ADC_DIV+1)
The duration of a multiplexer frame in CK32 cycles is:
MUX_Frame_Duration = 3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV[3:0]
The duration of a multiplexer frame in CK_FIR cycles is:
MUX frame duration (CK_FIR cycles) =
[3-2*PLL_FAST + Time_Slot_Duration * MUX_DIV] * (48+PLL_FAST*102)
The ADC conversion sequence is programmable through the MUXx_SEL control fields (I/O RAM 0x2100
to 0x2105). As stated above, there are three ADC time slots in the 71M6541D/F and four ADC time slots
in the 71M6542F, as set by MUX_DIV[3:0] (I/O RAM 0x2100[7:4]). In the expression MUXx_SEL[3:0] = n, ‘x’
refers to the multiplexer frame time slot number and n refers to the desired ADC input number or ADC handle
(i.e., ADC0 to ADC10, or simply 0 to 10 decimal). Thus, there are a total of 11 valid ADC handles in the
71M654x devices. For example, if MUX0_SEL[3:0] = 0, then ADC0, corresponding to the sample from the
IAP-IAN input (configured as a differential input), is positioned in the multiplexer frame during time slot 0. See
particular CE code.
Note that when the remote sensor interface is enabled, and even though the samples corresponding to
the remote sensor current (IBP-IBN) do not pass through the multiplexer, the MUX2_SEL[3:0] and
MUX3_SEL[3:0] control fields must be written with a valid ADC handle that is not being used. Typically,
ADC1 is used for this purpose (see Table 2). In this manner, the ADC1 handle, which is not used in the
71M6541D/F or 71M6542F, is used as a place holder in the multiplexer frame, in order to generate the
correct multiplexer frame sequence and the correct sample rate. The resulting sample data stored in
CE RAM 0x1 is undefined and is ignored by the CE code. Meanwhile, the digital isolation interface takes
care of automatically storing the samples for the remote interface current (IBP-IBN) in CE RAM 0x2.
Delay compensation and other functions in the CE code require the settings for MUX_DIV[3:0],
MUXx_SEL[3:0], RMT_E, FIR_LEN[1:0], ADC_DIV and PLL_FAST to be fixed for a given CE code.
71M6542F.
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| 71M6542G-IGTR/F | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
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