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参数资料
型号： 71M6542G-IGT/F
厂商： MAXIM INTEGRATED PRODUCTS INC
元件分类： 模拟信号调理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封装： LEAD FREE, LQFP-100
文件页数： 20/165页
文件大小： 2208K
代理商： 71M6542G-IGT/F
116
2008–2011 Teridian Semiconductor Corporation
v1.1
Name
Location
Rst Wk
Dir
Description
IE_XFER
IE_RTC1S
IE_RTC1M
IE_RTCT
IE_SPI
IE_EEX
IE_XPULSE
IE_YPULSE
IE_WPULSE
IE_VPULSE
SFR E8[0]
SFR E8[1]
SFR E8[2]
SFR E8[4]
SFR F8[7]
SFR E8[7]
SFR E8[6]
SFR E8[5]
SFR F8[4]
SFR F8[3]
0
R/W
Interrupt flags for external interrupts 2 and 6. These flags monitor the source
of the int6 and int2 interrupts (external interrupts to the MPU core). These
flags are set by hardware and must be cleared by the software interrupt
handler. The IEX2 (SFR 0xC0[1]) and IEX6 (SFR 0xC0[5]) interrupt flags are
automatically cleared by the MPU core when it vectors to the interrupt
handler. IEX2 and IEX6 must be cleared by writing zero to their corresponding
bit positions in SFR 0xC0, while writing ones to the other bit positions that are
not being cleared.
INTBITS
2707[6:0]
–
R
Interrupt inputs. The MPU may read these bits to see the input to external
interrupts INT0, INT1, up to INT6. These bits do not have any memory and
are primarily intended for debug use.
LCD_ALLCOM
2400[3]
0
–
R/W
Configures SEG/COM bits as COM. Has no effect on pins whose LCD_MAP
bit is zero.
LCD_BAT
2402[7]
0
–
R/W Connects the LCD power supply to VBAT in all modes.
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
2401[5:0]
2402[5:0]
0
–
R/W
Identifies which segments connected to SEG23 and SEG22 should blink. 1
means ‘blink.’ The most significant bit corresponds to COM5, the least
significant, to COM0.
LCD_CLK[1:0]
2400[1:0]
0
–
R/W
Sets the LCD clock frequency. Note: fw = 32768 Hz
LCD_CLK LCD Clock Frequency
LCD_CLK
LCD Clock Frequency
00
9
2
W
f
= 64 Hz
10
7
2
W
f
= 256 Hz
01
8
2
W
f
= 128 Hz
11
6
2
W
f
= 512 Hz
LCD_DAC[4:0]
240D[4:0]
0
–
R/W
The LCD contrast DAC. This DAC controls the VLCD voltage and has an
output range of 2.5 V to 5 V. The VLCD voltage is
VLCD = 2.5 + 2.5 * LCD_DAC[4:0]/31
Thus, the LSB of the DAC is 80.6 mV. The maximum DAC output voltage is
limited by V3P3SYS, VBAT, and whether LCD_BSTE = 1.
LCD_E
2400[7]
0
–
R/W
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
ground as are the COM and SEG outputs if their LCD_MAP bit is 1.
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