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| 型号： | 71M6545-IGTR/F |
| 厂商： | Maxim Integrated |
| 文件页数： | 103/133页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 3PHASE 64LQFP |
| 标准包装： | 1,500 |
| 系列： | * |
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71M6545/71M6545H Data Sheet
5.4.7
CE Status and Control
The CE Status Word is useful for generating early warnings to the MPU ( Table 65 ). It contains sag warnings
for phase A, B, and C, as well as F0 , the derived clock operating at the fundamental input frequency. The
MPU can read the CE status word at every CE_BUSY interrupt. Since the CE_BUSY interrupt occurs at
the sample rate (i.e., 2520.6 Hz for MUX_DIV[3:0] =6 or 2184.5 Hz for MUX_DIV[3:0] =7), it is desirable to
minimize the computation required in the interrupt handler of the MPU.
Table 65: CESTATUS Register
CE Address
0x80
Name
CESTATUS
Description
See description of CESTATUS bits in Table 66 .
CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful
for generating an early power fail warning to initiate necessary data storage. CESTATUS represents the
status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in
CESTATUS is shown in Table 66.
Table 66: CESTATUS Bit Definitions
CESTATUS
bit
31:4
3
2
1
0
Name
Not Used
F0
SAG_C
SAG_B
SAG_A
Description
These unused bits are always zero.
F0 is a square wave at the exact fundamental input frequency.
Normally zero. Becomes one when VADC10 (VC) remains below SAG_THR
(CE RAM 0x24) for SAGCNT samples. Does not return to zero until VADC10
(VC) rises above SAG_THR .
Normally zero. Becomes one when VADC9 (VB) remains below SAG_THR
for SAG_CNT samples. Does not return to zero until VADC9 (VB) rises above
SAG_THR .
Normally zero. Becomes one when VADC8 (VA) remains below SAG_THR
for SAG_CNT samples. Does not return to zero until VADC8 (VA) rises above
SAG_THR .
The CE is initialized by the MPU using CECONFIG ( Table 67 ). This register contains in packed form
SAG_CNT, FREQSEL0, FREQSEL1, EXT_PULSE, PULSE_SLOW, and PULSE_FAST . The CECONFIG bit
definitions are given in Table 68 .
Table 67: CECONFIG Register
CE Address
0x20
Name
CECONFIG
Data
0x0030DA20
Description
See description of the CECONFIG bits in Table 68 .
The EXT_TEMP bit enables temperature compensation by the MPU, when set to 1. When 0, internal (CE)
temperature compensation is enabled.
The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by
the MPU if EXT _ PULSE = 1. In this case, the MPU controls the pulse rate by placing values into APULSEW and
APULSER (CE RAM 0x44 and 0x48) . By setting EXT _ PULSE = 0, the CE controls the pulse rate based on
WSUM_X (CE RAM 0x84) and VARSUM_X (CE RAM 0x88).
The 71M6545/H Demo Code creep function halts both internal and external pulse generation.
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