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| 型号： | 71M6545-IGTR/F |
| 厂商： | Maxim Integrated |
| 文件页数： | 98/133页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 3PHASE 64LQFP |
| 标准包装： | 1,500 |
| 系列： | * |
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71M6545/71M6545H Data Sheet
5.3
Reading the Info Page (71M6545H only)
High precision trim fuse values provided in the 71M6545H device cannot be directly accessed through the
I/O RAM space. These trim fuses reside in a special area termed the “Info Page”. The MPU gains access
to the Info Page by setting the INFO_PG ( I/O RAM 0x270B[0] ) control bit. Once the INFO_PG bit is set, Info
Page contents are accessible in program memory space based at the address specified by the contents
of CE_LCTN[5:0] ( I/O RAM 0x2109[5:0] ). CE_LCTN[5:0] specifies a base address at a 1KB address
boundary. Thus, the base address for the Info Page is at 1024* CE_LCTN[5:0]. Table 62 provides a list of
the available 71M6545H trim fuses and their corresponding offsets relative to the Info Page base
address. After reading the desired Info Page information, the MPU must reset the INFO_PG bit.
Table 62. Info Page Trim Fuses
Trim Fuse
TEMP_85[10:8]
TEMP_85[7:0]
(11-bits)
TRIMBGB[15:8]
TRIMBGB[7:0]
(16-bits)
TRIMBGD[7:0]
(8-bits)
Object Size
8-bits
8-bits
8-bits
8-bits
8-bits
Address Offset
0x90
0x91
0x92
0x93
0x94
Comments
TEMP_85[10:0] holds the
STEMP[10:0] reading at 85°C.
2’s complement format
TRIMBGB[15:0] holds the
deviation of VREF from its ideal
value (1.195V) at 85°C.
LSB = 0.1 mV
2’s complement format
TRIMBGD[7:0] holds the
deviation of VREF from its ideal
value (1.195V) at 22°C.
LSB = 0.1 mV
2’s complement format
Figure 33. Trim Fuse Bit Mapping
Offset
0x90
0x91
0x92
0x93
0x94
Name
TEMP_85[10:0]
TRIMBGB[15:0]
TRIMBGD[7:0]
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
TEMP_85[7:0]
TRIMBGB[15:8]
TRIMBGB[7:0]
TRIMBGD[7:0]
Bit 2 Bit 1 Bit 0
TEMP_85[10:8]
The code below provides an example for reading Info Page fuse trims. In this code example, the address,
"px" is a pointer to the MPU’s code space. In assembly language, the Info Page data objects, which are
read-only, must be accessed with the MOVC 8051 instruction.
In C, Info Page trim fuses must be fetched with a pointer of the correct width, depending whether an 8-bit
or a 16-bit data object is to be fetched. The case statements in the code example below perform casts to
obtain a pointer of the correct size for each object, as needed.
In assembly language, the MPU has to form 11-bit or 16-bit values from two separate 8-bit fetches,
depending on the object being fetched.
The byte values containing less than 8 valid bits are LSB justified. For example Info Page offset 0x90 is
an 8-bit object, whose three LSBs are bits [10:8] of the complete TEMP_85[10:0] 11-bit object. The Info
Page data objects are 2’s complement format and should be sign extended when read into a 16-bit data
type (see case _TEMP85 in the code example).
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相关代理商/技术参数 |
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