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| 型号： | 71M6545-IGTR/F |
| 厂商： | Maxim Integrated |
| 文件页数： | 55/133页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 3PHASE 64LQFP |
| 标准包装： | 1,500 |
| 系列： | * |
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71M6545/71M6545H Data Sheet
See 2.2.8.3 Control of the 71M6xx3 Isolated Sensor on page 22 for information on how to read the
STEMP[10:0] information from the 71M6xx3.
2.5.7
71M6545/H Battery Monitor
The 71M6545/H temperature measurement circuit can also monitor the battery at the VBAT_RTC pin.
When TEMP_BAT ( I/O RAM 0x28A0[4] ) is set, a battery measurement is performed as part of each
temperature measurement. The value of the battery reading is stored in register BSENSE[7:0] (I/O RAM
0x2885) . The following equations are used to calculate the voltage measured on the VBAT_RTC pin from
the BSENSE[7:0] and STEMP[10:0] values. The result of the equation below is in volts. In MSN mode,
TEMP_PWR = 1 use:
VBAT _ RTC = 3 . 3 V + ( BSENSE ? 142 ) ? 0 . 0246 V + STEMP ? 0 . 000297 V
In MSN mode, a 100 μA de-passivation load can be applied to the battery by setting the BCURR ( I/O RAM
0x2704[3] ) bit. Battery impedance can be measured by taking a battery measurement with and without
BCURR . Regardless of the BCURR bit setting, the battery load is never applied in SLP mode.
2.5.8
71M6xx3 VCC Monitor
The 71M6xx3 monitors its VCC pin voltage. The voltage of the VCC pin can be obtained by the 71M6545/H
by issuing a read command to the 71M6xx3. The 71M6545/H must request both the VSENSE[7:0] and
STEMP[10:0] values from the 71M6xx3. See the 71M6xxx Data Sheet for the equation to calculate the
71M6xx3 VCC pin voltage from the VSENSE[7:0] and STEMP[10:0] values read from the 71M6xx3.
See 2.2.8.3 Control of the 71M6xx3 Isolated Sensor on page 22 for information on how to read
VSENSE[7:0] and STEMP[10:0] from the 71M6xx3 remote sensors.
2.5.9
UART Interface
The 71M6545/H provides an asynchronous interface (UART). The UART can be used to connect to AMR
modules, user interfaces, etc., and also support a mechanism for programming the on-chip flash memory.
2.5.10 DIO Pins
On reset or power-up, all DIO pins are DIO inputs until they are configured for the desired configuration under
MPU control.
After reset or power up, pins DIO0 through DIO14 are initially DIO outputs, but are disabled by
PORT_E = 0 (I/O RAM 0x270C[5] ) to avoid unwanted pulses. After configuring pins DIO0 through
DIO14 the host enables the pins by setting PORT_E = 1.
DIO pins can be configured independently as an input or output. For DIO0 to DIO14, this is done with the
SFR registers P0 (SFR 0x80) , P1 (SFR 0x90) , P2 (SFR 0xA0) and P3 (SFR 0xB0) as shown in Table 44 .
Example: DIO12 (pin 19, gray fields in Table 44 ) is configured as a DIO output pin with a value of 1 (high)
by writing 1 to both P3[4]and P3[0] .
Table 44: Data/Direction Registers and Internal Resources for DIO0 to DIO14
DIO
Pin #
0
31
1
30
2
29
3
28
4
27
5
26
6
25
7
24
8
23
9
22
10
21
11
20
12
19
13
18
14
17
DIO Data Register
Direction Register:
0 = input, 1 = output
0
4
1 2
P0 (SFR80)
5 6
P0 (SFR80)
3
7
0
4
1 2
P1 (SFR90)
5 6
P1 (SFR90)
3
7
0
4
1 2
P2 (SFRA0)
5 6
P2 (SFRA0)
3
7
0 1 2
P3 (SFRB0)
4 5 6
P3 (SFRB0)
Internal Resources
Configurable
--
--
--
--
Y
Y
Y
Y
Y
Y
Y
Y
–
–
–
The configuration for pins DIO19 to DIO25, DIO28 and DIO29 are shown in Table 45
The configuration for pins DIO55 is shown in Table 46 .
v2
55
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