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| 型号： | 71M6545-IGTR/F |
| 厂商： | Maxim Integrated |
| 文件页数： | 38/133页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 3PHASE 64LQFP |
| 标准包装： | 1,500 |
| 系列： | * |
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71M6545/71M6545H Data Sheet
The rest of the slaves ignore the message. After addressing the slave, the host outputs the rest of the
message with the 9 th bit set to 0, so no additional serial port receive interrupts is generated.
UART Control Registers:
The functions of UART0 depend on the setting of the Serial Port Control Register S0CON shown in Table
18, and the PCON register shown in Table 19 .
Since the TI0 and RI0 bits are in an SFR bit addressable byte, common practice would be to
clear them with a bit operation, but this must be avoided . The hardware implements bit
operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after the
read, but before the write, its flag is cleared unintentionally.
The proper way to clear these flag bits is to write a byte mask consisting of all ones except
for a zero in the location of the bit to be cleared. The flag bits are configured in hardware to
ignore ones written to them.
Table 18: The S0CON (UART0) Register (SFR 0x98)
Bit
S0CON[7]
Symbol
SM0
Function
The SM0 and SM1 bits set the UART0 mode:
Mode
0
Description
N/A
SM0
0
SM1
0
S0CON[6]
SM1
1
2
3
8-bit UART
9-bit UART
9-bit UART
0
1
1
1
0
1
S0CON[5]
S0CON[4]
S0CON[3]
S0CON[2]
S0CON[1]
S0CON[0]
Bit
PCON[7]
SM20
REN0
TB80
RB80
TI0
RI0
Symbol
SMOD
Enables the inter-processor communication feature.
If set, enables serial reception. Cleared by software to disable reception.
The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,
depending on the function it performs (parity check, multiprocessor
communication etc.)
In Modes 2 and 3 it is the 9 th data bit received. In Mode 1, SM20 is 0, RB80 is the
stop bit. In mode 0, this bit is not used. Must be cleared by software.
Transmit interrupt flag; set by hardware after completion of a serial transfer. Must
be cleared by software (see Caution above).
Receive interrupt flag; set by hardware after completion of a serial reception. Must
be cleared by software (see Caution above).
Table 19: PCON Register Bit Description ( SFR 0x87 )
Function
The SMOD bit doubles the baud rate when set
2.4.8
Timers and Counters
The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured
for counter or timer operations.
In timer mode, the register is incremented every machine cycle, i.e., it counts up once for every 12 periods of
the MPU clock. In counter mode, the register is incremented when the falling edge is observed at the
corresponding input signal T0 or T1 (T0 and T1 are the timer gating inputs derived from certain DIO pins.
Since it takes 2 machine cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock
frequency (CKMPU). There are no restrictions on the duty cycle, however to ensure proper recognition of the
0 or 1 state, an input should be stable for at least 1 machine cycle.
Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 20 and Table 21 . The
TMOD ( SFR 0x89 ) register, shown in Table 22 , is used to select the appropriate mode. The timer/counter
operation is controlled by the TCON ( SFR 0x88 ) register, which is shown in Table 23 . Bits TR1 ( TCON[6] )
and TR0 ( TCON[4] ) in the TCON register start their associated timers when set.
38
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