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| 型号： | 71M6545-IGTR/F |
| 厂商： | Maxim Integrated |
| 文件页数： | 61/133页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 3PHASE 64LQFP |
| 标准包装： | 1,500 |
| 系列： | * |
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71M6545/71M6545H Data Sheet
Table 50: SPI Transaction Fields
Field
Name
Address
Command
Status
Data
Required
Yes, except
single byte
transaction
Yes
Yes, if transaction
includes DATA
Yes, if transaction
includes DATA
Size
(bytes)
2
1
1
1 or
more
Description
16-bit address. The address field is not required if the transaction
is a simple SPI command.
8-bit command. This byte can be used as a command to the
MPU. In multi-byte transactions, the MSB is the R/W bit. Unless
the transaction is multi-byte and SPI_CMD is exactly 0x80 or
0x00, the SPI_CMD register is updated and an SPI interrupt is
issued. Otherwise, the SPI_CMD register is unchanged and the
interrupt is not issued.
8-bit status field, indicating the status of the previous transaction.
This byte is also available in the MPU memory map as
SPI_STAT (I/O RAM 0x2708) . See Table 52 for the contents.
The read or write data. Address is auto incremented for each
new byte.
The SPI_STAT byte is output on every SPI transaction and indicates the parity of the previous transaction
and the error status of the previous transaction. Potential error sources are:
?
?
71M6545/H not ready
Transaction not ending on a byte boundary.
SPI Safe Mode
Sometimes it is desirable to prevent the SPI interface from writing to arbitrary RAM locations and thus
disturbing MPU and CE operation. This is especially true in AFE applications. For this reason, the SPI
SAFE mode was created. In SPI SAFE mode, SPI write operations are disabled except for a 16 byte
transfer region at address 0x400 to 0x40F. If the SPI host needs to write to other addresses, it must use
the SPI_CMD register to request the write operation from the MPU. SPI SAFE mode is enabled by the
SPI_SAFE bit (I/O RAM 0x270C[3]) .
Single-Byte Transaction
If a transaction is a single byte, the byte is interpreted as SPI_CMD. Regardless of the byte value,
single-byte transactions always update the SPI_CMD register and cause an SPI interrupt to be generated.
Multi-Byte Transaction
As shown in Figure 20 , multi-byte operations consist of a 16 bit address field, an 8 bit CMD, a status byte,
and a sequence of data bytes. A multi byte transaction is three or more bytes.
SERIAL READ
16 bit Address
8 bit CMD
Status Byte
DATA[ADDR]
DATA[ADDR+1]
(From Host) SPI_CSZ
Extended Read . . .
0
15
16
23
24
31
32
39
40
47
(From Host) SPI_CK
(From Host) SPI_DI
A15
A14
A1
A0
C7
C6
C5
C0
x
(From 6543) SPI_DO
HI Z
ST7
ST6
ST5
ST0
D7
D6
D1
D0
D7
D6
D1
D0
SERIAL WRITE
16 bit Address
8 bit CMD
Status Byte
DATA[ADDR]
DATA[ADDR+1]
(From Host) SPI_CSZ
Extended Write . . .
0
15
16
23
24
31
32
39
40
47
(From Host) SPI_CK
(From Host) SPI_DI
x
A15
A14
A1
A0
C7
C6
C5
C0
D7
D6
D1
D0
D7
D6
D1
D0
x
(From 6543) SPI_DO
HI Z
ST7
ST6
ST5
ST0
Figure 20: SPI Slave Port - Typical Multi-Byte Read and Write operations
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