- 您现在的位置：买卖IC网 > PDF目录20610 > 71M6545-IGTR/F (Maxim Integrated)IC ENERGY METER 3PHASE 64LQFP PDF资料下载
参数资料
| 型号： | 71M6545-IGTR/F |
| 厂商： | Maxim Integrated |
| 文件页数： | 63/133页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER 3PHASE 64LQFP |
| 标准包装： | 1,500 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页当前第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页
71M6545/71M6545H Data Sheet
operation is always based on a two-byte word, the initial address must always be even. Data is written to
the 16-bit flash memory bus after the odd word is written.
In SFM mode, the MPU is completely halted. For this reason, the interrupt feature described in the SPI
Transaction section above is not available in SFM mode. The 71M6545/H must be reset by the WD timer or
by the RESET pin in order to exit SFM mode.
Invoking SFM
The following conditions must be met prior to invoking SFM:
?
?
?
?
?
ICE_E = 1. This disables the watchdog and adds another layer of protection against inadvertent
Flash corruption.
The external power source (V3P3SYS, V3P3A) is at the proper level (> 3.0 VDC).
PREBOOT = 0 ( SFR 0xB2[7]) . This validates the state of the SECURE bit (SFR 0xB2[6]) .
SECURE = 0. This I/O RAM register indicates that SPI secure mode is not enabled. Operations are
limited to SFM Mass Erase mode if the SECURE bit = 1 (Flash read back is not allowed in Secure mode).
FLSH_UNLOCK[3:0] = 0010 ( I/O RAM 0x2702[7:4]) .
The I/O RAM registers SFMM ( I/O RAM 0x2080 ) and SFMS (I/O RAM 0x2081) are used to invoke SFM. Only
the SPI interface has access to these two registers. This eliminates an indirect path from the MPU for
disabling the watchdog. SFMM and SFMS need to be written to in sequence in order to invoke SFM. This
sequential write process prevents inadvertent entering of SFM. The sequence for invoking SFM is:
?
First, write to SFMM ( I/O RAM 0x2080 ) register. The value written to this register defines the SFM mode.
o
o
o
0xD1: Mass Erase mode. A Flash Mass erase cycle is invoked upon entering SFM.
0x2E: Flash Read back mode. SFM is entered for Flash read back purposes. Flash writes
are blocked and it is up to the user to guarantee that only previously unwritten locations are
written. This mode is not accessible when SPI secure mode is set.
SFM is not invoked if any other pattern is written to the SFMM register.
?
Next, write 0x96 to the SFMS ( I/O RAM 0x2081 ) register. This write invokes SFM provided that the
previous write operation to SFMM met the requirements. Writing any other pattern to this register
does not invoke SFM. Additionally, any write operations to this register automatically reset the
previously written SFMM register values to zero.
SFM Details
The following occurs upon entering SFM.
?
?
?
?
?
The CE is disabled.
The MPU is halted. Once the MPU is halted it can only be restarted with a reset. This reset can be
accomplished with the RESET pin, a watchdog reset, or by cycling power.
The Flash control logic is reset in case the MPU was in the middle of a Flash write operation or Erase
cycle.
Mass erase is invoked if specified in the SFMM (I/O RAM 0x2080) register (see Invoking SFM, above).
The SECURE bit ( SFR 0xB2[6] ) is cleared at the end of this and all Mass Erase cycles.
All SPI read and write operations now refer to Flash instead of XRAM space.
The SPI host can access the current state of the pending multi-cycle Flash access by performing a 4-byte
SPI write of any address and checking the status field.
All SPI write operations in SFM mode must be 6-byte write transactions that write two bytes to an even
address. The write transactions must contain a command byte of 0x00 which is the form that does not
create an MPU interrupt. Auto incrementing is disabled for write operations.
SPI read transactions can make use of auto increment and may access single bytes. The command byte
must always be 0x80 in SFM read transactions.
v2
63
相关PDF资料 |
PDF描述 |
|---|---|
| T95S224M035LZAL | CAP TANT 0.22UF 35V 20% 1507 |
| GBC12DCSN-S288 | CONN EDGECARD 24POS .100 EXTEND |
| 78M6612-M/F/P2 | IC PWR MEASUREMENT AC 68SQFN |
| V48C28H75BL2 | CONVERTER MOD DC/DC 28V 75W |
| ISL6613IRZ-T | IC MOSFET DRVR SYNC BUCK 10-DFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 71M6545T-IGT/F | 制造商:Maxim Integrated Products 功能描述:METROLOGY PROCESSORS - Rail/Tube |
| 71M6545T-IGTR/F | 制造商:Maxim Integrated Products 功能描述:3-PHASE AFE, 32KB FLASH, PRES TEMP SENSOR - Tape and Reel |
| 71M6601 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:On-Chip Temperature Sensor Enables Localized Digital Temperature On-Chip Power Monitoring |
| 71M6601-IF | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:On-Chip Temperature Sensor Enables Localized Digital Temperature On-Chip Power Monitoring |
| 71M6601-IL | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:On-Chip Temperature Sensor Enables Localized Digital Temperature On-Chip Power Monitoring |
发布紧急采购，3分钟左右您将得到回复。