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参数资料
| 型号： | 85C30 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | Enhanced Serial Communications Controller |
| 中文描述： | 增强的串行通信控制器 |
| 文件页数： | 10/68页 |
| 文件大小： | 528K |
| 代理商： | 85C30 |
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AMD
10
Am85C30
Data Path
The transmit and receive data path illustrated in Figure 2
is identical for both channels. The receiver has three
8-bit buffer registers in a FIFO arrangement, in addition
to the 8-bit receive shift register. This scheme creates
additional time for the CPU to service an interrupt at the
beginning of a block of high-speed data. Incoming data
are routed through one of several paths (data or CRC)
depending on the selected mode (the character length
in asynchronous modes also determines the data path).
The transmitter has an 8-bit transmit data buffer register
loaded from the internal data bus and a 20-bit transmit
shift register that can be loaded either from the sync-
character registers or from the transmit data register.
Depending on the operational mode, outgoing data are
routed through one of four main paths before they are
transmitted from the Transmit Data output (TxD).
Table 1. Read and Write Register Functions
Write Register Functions
RR0
Transmit/Receive buffer status and External
status
RR1
Special Receive Condition status
(also 10
×
19 bit FIFO Frame Reception Status if
WR15 bit D
2
is set)
RR2
Modified interrupt vector
(Channel B only)
Unmodified interrupt vector
(Channel A only)
RR3
Interrupt Pending bits
(Channel A only)
RR6
LSB Byte Count (14-bit counter)
(if WR15 bit D
2
set)
RR7
MSB Byte Count (14-bit counter)
and 10
×
19 bit FIFO Status (if WR15 bit D
2
is set)
RR8
Receive buffer
RR10
Miscellaneous XMTR, RCVR status
RR12
Lower byte of baud rate generator time constant
RR13
Upper byte of baud rate generator time constant
RR15
External/Status interrupt information
WR0
Command Register, Register Pointers CRC
initialize, initialization commands for the various
modes, shift right/shift left command
Interrupt conditions and data transfer mode
definition
Interrupt vector (accessed through either channel)
Receive parameters and control
Transmit/Receive miscellaneous parameters and
modes
Transmit parameters and controls
Sync character or SDLC address field
Sync character or SDLC flag
SDLC/HDLCenhancements(if bitD
0
of WR15 is
set)
Transmit buffer
Master interrupt control and reset (accessed
through either channel)
Miscellaneous transmitter/receiver control bits,
data encoding
Clock mode control, Rx and Tx clock source
Lower byte of baud rate generator time constant
Upper byte of baud rate generator time constant
Miscellaneous control bits, DPLL control
External/Status interrupt control
WR1
WR2
WR3
WR4
WR5
WR6
WR7
WR7
′
WR8
WR9
WR10
WR11
WR12
WR13
WR14
WR15
Read Register Functions
Write Register Functions
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