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参数资料
型号： 85C30
厂商： Advanced Micro Devices, Inc.
英文描述： Enhanced Serial Communications Controller
中文描述： 增强的串行通信控制器
文件页数： 27/68页
文件大小： 528K
代理商： 85C30
AMD
27
Am85C30
7
6
5
4
3
2
1
0
FOY FDA
BC
13
BC
12
BC
11
BC
10
BC
9
BC
8
RR7
FIFO Data Available Status
1 = Status Reads Will Come From FIFO
0 = Status Reads Will Come From SCC
FIFO Overflow Status
1 = FIFO Overflowed During Operation
0 = Normal
BC
7
BC
BC
BC
BC
BC
BC
BC
RR6
Read From FIFO
LSB Byte Count
RR15
ENH
FEN
Status FIFO Enable Control Bit
1 = Status and Byte Count Will be
Held in the Status FIFO Until Read
0 = Status Will Not be Held (SCC Emulation Mode)
= No Change From NMOS SCC DFN
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
ENH: SDLC/HDLC Enhancement Status
1 = Enhancements Enabled
0 = Enhancements Disabled
Figure 15. SCC Additional Registers
10216F-19
Enable
The byte counter is enabled when the SCC is in the
SDLC/HDLC mode and WR15 bit 2 is set to 1.
Reset
The byte counter is reset whenever an SDLC flag char-
acter is received. The reset is timed so that the contents
of the byte counter are successfully written into the
FIFO.
Increment
The byte counter is incremented by writes to the data
FIFO. The counter represents the number of bytes re-
ceived by the SCC, rather than the number of bytes
transferred from the SCC. (These counts may differ by
up to the number of bytes in the receive data FIFO con-
tained in the SCC.)
Am85C30 SDLC/HDLC Enhancement
Register Access
SDLC/HDLC enhancements on the Am85C30 are en-
abled or disabled via bits D
2
or D
0
in WR15. Bit D
2
deter-
mines whether or not the 10
×
19 bit SDLC/HDLC
frame status FIFO is enabled while bit D
0
determines
whether or not other enhancements are enabled via
WR7
′
. Table 3 shows what functions on the Am85C30
are enabled when these bits are set.
When bit D
2
of WR15 is set to 1, two additional registers
(RR6 and RR7) per channel specific to the 10
×
19 bit
Frame Status FIFO are made available. The Am85C30
register map when this function is enabled is shown in
Table 4.
Bit D
0
of WR15 determines whether or not other en-
hancements pertinent only to SDLC/HDLC mode opera-
tion are available for programming via WR7
′
as shown
below. Write Register 7 prime (WR7
′
) can be written to
when bit D
0
of WR15 is set to 1. When this bit is set, writ-
ing to WR7 (flag register) actually writes to WR7
′
. If bit
D
6
of this register is set to 1, previously unreadable reg-
isters WR3, WR4, WR5, and WR10 are readable by the
pro-cessor. In addition, WR7
′
is also readable by having
this bit set. WR3 is read when a bogus RR9 register is
accessed during a read cycle. WR10 is read by access-
ing RR11, and WR7
′
is accessed by executing a read to
RR14. The Am85C30 register map with bit D
0
of WR15
and bit D
6
of WR7
′
set is shown in Table 5.
If both bits D
0
and D
2
of WR15 are set to 1 and D
6
of
WR7
′
is set to 1, then the Am85C30 register map is as
shown in Table 6.
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