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参数资料
| 型号： | 85C30 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | Enhanced Serial Communications Controller |
| 中文描述： | 增强的串行通信控制器 |
| 文件页数： | 14/68页 |
| 文件大小： | 528K |
| 代理商： | 85C30 |
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AMD
14
Am85C30
When a secondary station has a message to transmit
and recognizes an EOP on the line, it changes the last
binary 1 of the EOP to a 0 before transmission. This has
the effect of turning the EOP into a flag sequence. The
secondary station now places its message on the loop
and terminates the message with an EOP. Any secon-
dary stations farther down the loop with messages to
transmit can then append their messages to the mes-
sage of the first secondary station by the same process.
Any secondary stations without messages to send
merely echo the incoming messages and are prohibited
from placing messages on the loop (except upon recog-
nizing an EOP).
SDLC Loop mode is a programmable option in the
ESCC. NRZ, NRZI, and FM coding may all be used in
SDLC Loop mode.
Baud Rate Generator
Each channel in the ESCC contains a programmable
baud rate generator. Each generator consists of two
8-bit time constant registers that form a 16-bit time con-
stant, a 16-bit down counter, and a flip-flop on the output
producing a square wave. On start-up, the flip-flop on
the output is set in a High state, the value in the time con-
stant register is loaded into the counter, and the counter
starts counting down. The output of the baud rate gen-
erator toggles upon reaching zero; the value in the time
constant register is loaded into the counter, and the
process is repeated. The time constant may be changed
at any time, but the new value does not take effect until
the next load of the counter.
The output of the baud rate generator may be used as
either the transmit clock, the receive clock, or both. It
can also drive the digital phase-locked loop (see next
section).
If the receive clock or transmit clock is not programmed
to come from the
TRxC
pin, the output of the baud rate
generator may be echoed out via the
TRxC
pin.
The following formula relates the time constant to the
baud rate where PCLK or
RTxC
is the baud rate genera-
tor input frequency in Hz. The clock mode is X1, X16,
X32, or X64 as selected in Write Register 4, bits D
6
and
D
7
. Synchronous operation modes should select X1 and
asynchronous should select X16, X32, or X64.
Time Constant =
PCLK or RTxC Frequency
2 (Baud Rate)(Clock Mode)
– 2
The following formula relates the time constant to the
baud rate. The baud rate is in bits/second.
Baud Rate =
2
×
(Clock Mode)
×
(Time Constant + 2)
PCLK or RTxC Frequency
Time Constant Values
for Standard Baud Rates at BR Clock
= 3.9936 MHz
Rate
(Baud)
Time Constant
(decimal/Hex notation)
Error
19200
9600
7200
4800
3600
2400
2000
1800
1200
600
300
150
134.5
110
75
50
102
206
275
414
553
830
996
1107
1662
3326
6654
13310
14844
18151
26622
39934
(0066)
(00CE)
(0113)
(019E)
(0229)
(033E)
(03E4)
(0453)
(067E)
(0CFE)
(19FE)
(33FE)
(39FC)
(46E7)
(67FE)
(98FE)
0
0
0.12%
0
0.06%
0
0.04%
0.03%
0
0
0
0
0.0007%
0.0015%
0
0
Digital Phase-Locked Loop
The ESCC contains a digital phase-locked loop (DPLL)
to recover clock information from a data stream with
NRZI or FM encoding. The DPLL is driven by a clock that
is nominally 32 (NRZI) or 16 (FM) times the data rate.
The DPLL uses this clock, along with the data stream, to
construct a clock for the data. This clock may then be
used as the SCC receive clock, the transmit clock,
or both.
For NRZI encoding, the DPLL counts the 32X clock to
create nominal bit times. As the 32X clock is counted,
the DPLL is searching the incoming data stream for
edges (either 1/0 or 0/1). As long as no transitions are
detected, the DPLL output will be free running and its in-
put clock source will be divided by 32, producing an out-
put clock without any phase jitter. Upon detecting a
transition the DPLL will adjust its clock output (during the
next counting cycle) by adding or subtracting a count of
1, thus producing a terminal count closer to the center of
the bit cell. The adding or subtracting of a count of 1 will
produce a phase jitter of
±
5.63
°
on the output of the
DPLL. Because the SCC’s DPLL uses both edges of the
incoming signal to compare with its clock source, the
mark-space ratio (50%) of the incoming signal should
not deviate by more than
±
1.5% if proper locking is to
occur.
For FM encoding, the DPLL still counts from 0 to 31, but
with a cycle corresponding to two bit times. When the
DPLL is locked, the clock edges in the data stream
should occur between counts 15 and 16 and between
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