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参数资料
| 型号： | 85C30 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | Enhanced Serial Communications Controller |
| 中文描述： | 增强的串行通信控制器 |
| 文件页数： | 62/68页 |
| 文件大小： | 528K |
| 代理商： | 85C30 |
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A M E N D M E N T
AMD
9
Am85C30
SWITCHING CHARACTERISTICS over COMMERCIAL operating range (continued)
Interrupt Acknowledge Timing, Reset Timing, Cycle Timing (see Figures 22–24)
27
TdA(DR)
Address Required Valid to Read
Data Valid Delay
WR
Low Width
WR
↓
to Write Data Valid
Write Data to
WR
↑
Hold Time
WR
↓
to Wait Valid Delay (Note 2)
RD
↓
to Wait Valid Delay (Note 2)
WR
↓
to
W
/
REQ
Not Valid Delay
RD
↓
to
W
/
REQ
Not Valid Delay
WR
↓
to
DTR
/
REQ
Not Valid Delay
WR
↓
to
DTR
/
REQ
Not Valid Delay
RD
↑
to
DTR
/
REQ
Not Valid Delay
PCLK
↓
to
INT
Valid Delay (Note 2)
INTACK
to
RD
↓
(Acknowledge)
Delay (Note 3)
RD
(Acknowledge) Width
RD
↓
(Acknowledge) to Read
Data Valid Delay
IEI to
RD
↓
(Acknowledge) Setup
Time
IEI to
RD
↑
(Acknowledge) Hold
Time
IEI to IEO Delay Time
PCLK
↑
to IEO Delay
RD
↓
to
INT
Inactive Delay (Note 2)
RD
↑
to
WR
↓
Delay for No Reset
WR
↑
to
RD
↓
Delay for No Reset
WR
and
RD
Coincident Low for
Reset
Valid Access Recovery Time
(Note 1)
220
160
100
90
ns
28
29
30
31
32
33
34
35a
35b
36
37
38
TwWRI
TdWRf(DW)
ThDW(WR)
TdWR(W)
TdRD(W)
TdWRf(REQ)
TdRDf(REQ)
TdWRr(REQ)
TdWRr(EREQ)
TdRDr(REQ)
TdPC(INT)
TdIAi(RD)
150
125
75
65
ns
ns
ns
ns
ns
ns
ns
35
35
20
20
0
0
0
0
170
170
170
170
4TcPc
120
NA
500
100
100
120
120
4TcPc
120
NA
400
50
50
70
70
50
50
65
65
4TcPc
70
NA
175
4TcPc ns
65
NA
160
ns
ns
ns
ns
150
125
50
45
39
40
TwRDA
TdRDA(DR)
150
125
75
65
ns
ns
140
120
70
60
41
TsIEI(RDA)
95
80
50
45
ns
42
ThIEI(RDA)
0
0
0
0
ns
43
44
45
46
47
48
TdIEI(IEO)
TdPC(IEO)
TdRDA(INT)
TdRD(WRQ)
TdWRQ(RD)
TwRES
95
200
450
80
175
320
45
80
200
40
70
180
ns
ns
ns
ns
ns
ns
15
15
150
15
15
100
10
10
75
10
10
65
49
Trc
3.5
3.5
3.5
3.5
Notes:
1
Parameter applies only between transactions involving the ESCC, if
WR/RD
falling edge is synchronized to PCLK
falling edge, then TrC = 3TcPc.
2. Open-drain output, measured with open-drain test load.
3. Parameter is system dependent. For any SCC in the daisy chain, TdIAi(RD) must be greater than the sum of DdPC(IEO)
for the highest priority device in the daisy chain, TsIEI(RDA) for the SCC, and TdIEI(IEO) for each device separating
them in the daisy chain.
4. Parameter applies to Enhanced Request mode only.
No.
Parameter
Symbol
Parameter
Description
10 MHz
20 MHz
Min
Max
Min
Max Unit
8.192 MHz
Min
Max
Min
Max
16.384 MHz
TcPc
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