- 您现在的位置：买卖IC网 > PDF目录378244 > 85C30 (Advanced Micro Devices, Inc.) Enhanced Serial Communications Controller PDF资料下载
参数资料
| 型号： | 85C30 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | Enhanced Serial Communications Controller |
| 中文描述： | 增强的串行通信控制器 |
| 文件页数： | 7/68页 |
| 文件大小： | 528K |
| 代理商： | 85C30 |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页
AMD
7
Am85C30
PIN DESCRIPTION
Bus Timing and Reset
RD
Read (Input; Active Low)
This signal indicates a Read operation and, when the
SCC is selected, enables the SCC’s bus drivers. During
the Interrupt Acknowledge cycle, this signal gates the
interrupt vector onto the bus if the SCC is the highest pri-
ority device requesting an interrupt.
WR
Write (Input; Active Low)
When the SCC is selected, this signal indicates a Write
operation. The coincidence of
RD
and
WR
is interpreted
as a reset.
Channel Clocks
RTxCA
,
RTxCB
Receive/Transmit Clocks (Inputs; Active Low)
These pins can be programmed in several different
modes of operation. In each channel,
RTxC
may supply
the receive clock, the transmit clock, the clock for the
baud rate generator, or the clock of the digital phase-
locked loop. These pins can also be programmed for
use with the respective
SYNC
pins as a crystal oscilla-
tor. The receive clock may be 1, 16, 32, or 64 times the
data rate in asynchronous modes.
TRxCA
,
TRxCB
Transmit/Receive Clocks
(Inputs/Outputs; Active Low)
These pins can be programmed in several different
modes of operation.
TRxC
may supply the receive clock
or the transmit clock in the input mode or supply the out-
put of the digital phase-locked loop, the crystal oscilla-
tor, the baud rate generator, or the transmit clock in the
output mode.
Channel Controls for Modem, DMA,
or Other
CTSA
,
CTSB
Clear to Send (Inputs; Active Low)
If these pins are programmed as Auto Enables, a Low
on these inputs enables their respective transmitters. If
not programmed as Auto Enables, they may be used as
general-purpose inputs. Both inputs are Schmitt-trigger
buffered to accommodate slow rise-time inputs. The
SCC detects pulses on these inputs and may interrupt
the CPU on both logic level transitions.
DCDA
,
DCDB
Data Carrier Detect (Inputs; Active Low)
These pins function as receiver enables if they are pro-
grammed as Auto Enables; otherwise, they may be
used as general-purpose input pins. Both are Schmitt-
trigger buffered to accommodate slow rise-time signals.
The SCC detects pulses on these pins and may interrupt
the CPU on both logic level transitions.
DTR
/
REQA
,
DTR
/
REQB
Data Terminal Ready/Request
(Outputs; Active Low)
These outputs follow the inverted state programmed
into the DTR bit in WR5. They can also be used as
general-purpose outputs or as Request Lines for a DMA
controller.
RTSA
,
RTSB
Request to Send (Outputs; Active Low)
When the Request to Send (RTS) bit in Write Register 5
is set, the
RTS
signal goes Low. When the RTS bit is re-
set in the asynchronous mode and Auto Enable is on,
the signal goes High after the transmitter is empty. In
SYNC mode, or in asynchronous mode with Auto En-
able off, the
RTS
pins strictly follow the inverted state of
the RTS bit. Both pins can be used as general-purpose
outputs.
In SDLC mode, the AUTO RTS RESET enhancement
described later in this document brings
RTS
High after
the last 0 of the closing flag leaves the TxD pin.
SYNCA
,
SYNCB
Synchronization
(Inputs/Outputs; Active Low)
These pins can act either as inputs, outputs, or part of
the crystal oscillator circuit. In the Asynchronous Re-
ceive mode (crystal oscillator option not selected), these
pins are inputs similar to
CTS
and
DCD
. In this mode,
transitions on these lines affect the state of the Sync/
Hunt status bits in Read Register 0 but have no other
function.
In External Synchronization mode with the crystal
oscillator not selected, these lines also act as inputs.
In this mode,
SYNC
must be driven Low two receive
clock cycles after the last bit in the SYNC character is
received. Character assembly begins on the rising edge
of the receive clock immediately preceding the activa-
tion of
SYNC
.
In the Internal Synchronization mode (Monosync and
Bisync) with the crystal oscillator not selected, these
pins act as outputs and are active only during the part of
the receive clock cycle in which SYNC characters are
recognized. The SYNC condition is not latched, so
these outputs are active each time a SYNC pattern is
recognized (regardless of character boundaries). In
SDLC mode, these pins act as outputs and are valid on
receipt of a flag.
相关PDF资料 |
PDF描述 |
|---|---|
| 85C72 | 1K CMOS Serial EEPROM(1K位,5.0V CMOS串行EEPROM) |
| 85C82 | 2K CMOS Serial EEPROM(2K位,5.0V CMOS串行EEPROM) |
| 85C92 | 4K CMOS Serial EEPROM(4K位,5.0V CMOS串行EEPROM) |
| 85CNQ015APBF | SCHOTTKY RECTIFIER New GenIII D-61 Package |
| 85CNQ015ASMPBF | SCHOTTKY RECTIFIER New GenIII D-61 Package |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 85C5122DVB-RDTUM | 功能描述:开发板和工具包 - 8051 RAM Indus Green RoHS:否 制造商:Silicon Labs 产品:Development Kits 工具用于评估:C8051F960, Si7005 核心: 接口类型:USB 工作电源电压: |
| 85C51SND3B1 | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface |
| 85C51SND3B1N-7FTUL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface |
| 85C51SND3B1N-RTTUL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface |
| 85C51SND3B1N-UL | 制造商:ATMEL 制造商全称:ATMEL Corporation 功能描述:Single-Chip Digital Audio Decoder - Encoder with USB 2.0 Interface |
发布紧急采购，3分钟左右您将得到回复。