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参数资料
型号： 85C30
厂商： Advanced Micro Devices, Inc.
英文描述： Enhanced Serial Communications Controller
中文描述： 增强的串行通信控制器
文件页数： 47/68页
文件大小： 528K
代理商： 85C30
AMD
47
Am85C30
1
2
3
TdPC(REQ)
TdPC(W)
TsRXC(PC)
PCLK
↓
to
W/REQ
Valid Delay
PCLK
↓
to Wait Inactive Delay
RxC
↑
to PCLK
↑
Setup Time
(Notes 1, 4 & 8)
RxD to
RxC
↑
Setup Time
(Xl Mode) (Note 1)
RxD to
RxC
↑
Hold Time
(Xl Mode) (Note 1)
RxD to
RxC
↓
Setup Time
(Xl Mode) (Notes 1, 5)
RxD to
RxC
↓
Hold Time
(Xl Mode) (Notes 1, 5)
SYNC
to
RxC
↑
Setup Time
(Note 1)
SYNC
to
RxC
↑
Hold Time
(Note 1)
TxC
↓
to PCLK
↑
Setup Time
(Notes 2, 4 & 8)
TxC
↓
to TxD Delay (Xl Mode)
(Note 2)
TxC
↑
to TxD Delay (Xl Mode)
(Notes 2, 5)
TxD to
TRxC
Delay
(Send Clock Echo)
RTxC
High Width (Note 6)
RTxC
High Width (Note 9)
RTxC
Low Width (Note 6)
RTxC
Low Width (Note 9)
RTxC
Cycle Time (Notes 6, 7)
RTxC
Cycle Time (Note 9)
Crystal Oscillator Period (Note 3)
TRxC
High Width (Note 6)
TRxC
Low Width (Note 6)
TRxC
Cycle Time (Notes 6, 7)
DCD
or
CTS
Pulse Width
SYNC
Pulse Width
250
350
NA
150
250
NA
80
180
NA
ns
ns
NA
NA
NA
4
TsRXD(RXCr)
0
0
0
ns
5
ThRXD(RXCr)
150
125
50
ns
6
TsRXD(RXCf)
0
0
0
ns
7
ThRXD(RXCf)
150
125
50
ns
8
TsSY(RXC)
–200
–150
–100
ns
9
ThSY(RXC)
5TcPC
5TcPC
5TcPc
ns
10
TsTXC(PC)
NA
NA
NA
11
TdTXCf(TXD)
200
150
80
ns
12
TdTXCr(TXD)
200
150
80
ns
13
TdTXD(TRX)
200
140
80
ns
14a
14b
15a
15b
16a
16b
17
18
19
20
21
22
TwRTXh
TwRTxh(E)
TwRTXI
TwRTXl(E)
TcRTX
TcRTx(E)
TcRTXX
TwTRXh
TwTRXI
TcTRX
TwEXT
TwSY
150
50
150
50
488
125
125
150
150
488
200
200
120
40
120
40
400
100
100
120
120
400
120
120
80
15.6
80
15.6
244
31.25
62
80
80
244
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1000
1000
1000
SWITCHING CHARACTERISTICS
over MILITARY/INDUSTRIAL operating range
General Timing (see Figure 19)
Notes:
1.
RxC
is
RTxC
or
TRxC
, whichever is supplying the receive clock.
2.
TxC
is
TRxC
or
RTxC,
whichever is supplying the transmit clock.
3. Both
RTxC
and
SYNC
have 30-pF capacitors to ground connected to them.
4. Parameter applies only if the data rate is one-fourth the PCLK rate. In all other cases, no phase relationship between
RxC
and PCLK or
TxC
and PCLK is required.
5. Parameter applies only to FM encoding/decoding.
6. Parameter applies only for transmitter and receiver; DPLL and baud rate generator timing requirements are identical to
chip PCLK requirements.
7. The maximum receive or transmit data is 1/4 PCLK.
8. External PCLK to
RxC
or
TxC
synchronization requirement eliminated for PCLK divide-by-four operation.
TRxC
and
RTxC
rise and fall times are identical to PCLK. Reference timing specs Tfpc and Trpc.
Tx and Rx input clock slow rates should be kept to a maximum of 30 ns. All parameters related to input CLK edges
should be referenced at the point at which the transition begins or ends, whichever is the worst case.
9. ENHANCED FEATURE—
RTxC
used as input to internal DPLL only.
No.
Parameter
Symbol
Parameter
Description
10 MHz
16.384 MHz
Min
Max
Min
Max
Unit
8.192 MHz
Min
Max
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