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参数资料
| 型号： | 85C30 |
| 厂商： | Advanced Micro Devices, Inc. |
| 英文描述： | Enhanced Serial Communications Controller |
| 中文描述： | 增强的串行通信控制器 |
| 文件页数： | 12/68页 |
| 文件大小： | 528K |
| 代理商： | 85C30 |
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AMD
12
Am85C30
DETAILED DESCRIPTION
The functional capabilities of the ESCC can be de-
scribed from two different points of view: as a data com-
munications device, it transmits and receives data in a
wide variety of data communications protocols; as a mi-
croprocessor peripheral, it interacts with the CPU and
provides vectored interrupts and handshaking signals.
Data Communications Capabilities
The ESCC provides two independent full-duplex
channels programmable for use in any common
asynchronous or SYNC data-communication protocol.
Figure 3 and the following description briefly detail these
protocols.
Asynchronous Modes
Transmission and reception can be accomplished inde-
pendently on each channel with 5 to 8 bits per character,
plus optional even or odd parity. The transmitters can
supply 1, 1 1/2, or 2 stop bits per character and can pro-
vide a break output at any time. The receiver break-
detection logic interrupts the CPU both at the start and at
the end of a received break. Reception is protected from
spikes by a transient spike-rejection mechanism that
checks the signal one-half a bit time after a Low level is
detected on the receive data input. If the Low does not
persist (as in the case of a transient), the character as-
sembly process does not start.
Framing errors and overrun errors are detected and
buffered together with the partial character on which
they occur. Vectored interrupts allow fast servicing of
error conditions using dedicated routines. Furthermore,
a built-in checking process avoids the interpretation of
framing error as a new start bit; a framing error results in
the addition of one-half a bit time to the point at which the
search for the next start bit begins.
The ESCC does not require symmetric transmit and
receive clock signals—a feature allowing use of the
wide variety of clock sources. The transmitter and re-
ceiver can handle data at a rate of 1, 1/16, 1/32, or 1/64
of the clock rate supplied to the receive and transmit
clock inputs. In asynchronous modes, the
SYNC
pin
may be programmed as an input used for functions,
such as monitoring a ring indicator.
Synchronous Modes
The ESCC supports both byte-oriented and bit-oriented
synchronous communication. SYNC byte-oriented pro-
tocols can be handled in several modes, allowing char-
acter synchronization with a 6-bit or 8-bit SYNC
character (Monosync), any 12-bit or 16-bit SYNC pat-
tern (Bisync), or with an external SYNC signal. Leading
SYNC characters can be removed without interrupting
the CPU.
5- or 7-bit SYNC characters are detected with 8- or
16-bit patterns in the ESCC by overlapping the larger
pattern across multiple incoming SYNC characters as
shown in Figure 4.
CRC checking for Synchronous byte-oriented modes is
delayed by one character time so that the CPU may dis-
able CRC checking on specific characters. This permits
the implementation of protocols, such as IBM BISYNC.
Both CRC-16 (X
16
+ X
15
+ X
2
+ 1) and CCITT (X
16
+ X
12
+
X
5
+ 1) error-checking polynomials are supported.
Either polynomial may be selected in BISYNC and
MONO-SYNC modes. Users may preset the CRC gen-
erator and checker to all 1s or all 0s. The ESCC also pro-
vides a feature that automatically transmits CRC data
when no other data are available for transmission. This
allows for high-speed transmissions under DMA control
Parity
Start
Stop
Marking Line
Marking Line
Asynchronous
Monosync
Bisync
External Sync
SDLC/HDLC
×
25
Sync
Data
Data
CRC
1
CRC
2
Sync
Sync
Data
Data
CRC
1
CRC
2
Data
Data
CRC
1
CRC
2
Signal
Flag
Address
Information
Flag
CRC
2
CRC
1
Data
Data
Data
Figure 3. SCC Protocols
10216F-7
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