参数资料
型号: A3942KLGTR-T
厂商: Allegro Microsystems Inc
文件页数: 10/20页
文件大小: 0K
描述: IC GATE DVR QUAD HISIDE 38-TSSOP
标准包装: 8,000
配置: 高端
输入类型: SPI
延迟时间: 600ns
电流 - 峰: 15mA
配置数: 4
输出数: 4
电源电压: 4.5 V ~ 60 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 38-TFSOP(0.173",4.40mm 宽)
供应商设备封装: 38-TSSOP
包装: 带卷 (TR)
A3942
Quad High-Side Gate Driver
for Automotive Applications
Serial Port Registers Description
There are two 8-bit registers served by the serial port,
the Input register and the Output Fault register. The
time for the V DS monitor, according to the following
table:
structure of the registers is shown in the table at the
bottom of this page. The function of each bit in the
registers is described in this section.
Input Register
D2
0
0
1
D1
0
1
0
t ON Selected
t ON(00) *
t ON(01)
t ON(10)
D0 Gate On/Off Bit This bit is used to control the gate
drive output. It is logically ORed with the signal on
the discrete input pin, INx, corresponding to each of
1 1
*default state at device power-on
t ON(11)
the four channels, according to the following table:
D3 Clear Faults Bit This bit is used to clear a latched
Bit D0
0
0
1
1
ORed Settings
Pin INx
0
1
0
1
Result on
Gx Pin
Off
On
On
On
fault. After the fault is cleared, the gate output can
again follow the input logic to determine if the fault is
still present. Faults are cleared on a channel specific
basis.
D4 Mask Off-State Faults Bit [See asterisks (*) in
the table below.] When the application requires that
D1, D2 Short-to-Ground (STG) Turn-On Blank Time
MSB and LSB Bits The blank time, t on(xx) , delay
allows switching transients to settle before the A3942
STG function checks for a short. For each individual
channel, the combination of these bits sets the wait
Serial Port Bit Definition All bits active high, except WriteZ
Register
Short-to-Battery (STB) and Open Load (OL) faults be
checked primarily before output is enabled for the first
time, this bit can be used to allow STB and Open Load
faults to be ignored during normal operation (Short-to-
Ground faults can not be masked). This bit is applied
Bits
D7
D6
D5
D4
D3
D2
D1
D0
Input
Output Fault
Address MSB
Address MSB
Address LSB
Address LSB
Input Read
Enable
WriteZ
Mask
Off-State Faults (*)
Charge Pump
UVLO
Clear Faults
Thermal
Warning
STG Blank
Time MSB
Open Load
Fault (*)
STG Blank
Time LSB
STB Fault (*)
Gate
On/Off
STG Fault
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
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