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| 型号： | A3942KLGTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 13/20页 |
| 文件大小： | 0K |
| 描述： | IC GATE DVR QUAD HISIDE 38-TSSOP |
| 标准包装： | 8,000 |
| 配置： | 高端 |
| 输入类型： | SPI |
| 延迟时间： | 600ns |
| 电流 - 峰： | 15mA |
| 配置数： | 4 |
| 输出数： | 4 |
| 电源电压： | 4.5 V ~ 60 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
A3942
RESETZ Master Reset and Sleep Mode Pulsing this
pin low clears all latched faults in the channel-specific
fault registers. It also clears the serial port registers
(they return to their default values). When RESETZ is
held low long enough (t > t SLEEP ) the A3942 goes to
sleep, as described in the Sleep topic in the Functional
Description section.
ENB Enable Set low to actively pull low all outputs.
FAULTZ Fault Active low open drain output. Signals a
fault. Allows parallel connection with FAULTZ sig-
nals from other devices when required.
SCLK SPI Clock See Serial Port Operation topic in
Functional Description section.
CSZ SPI Chip Select input.
SDO SPI Data Output connection.
SDI SPI Data Input connection.
IREF Current Reference Defines the current used
as a reference to set gate drive currents, diagnostic
currents and internal timers. A resistor, RREF, con-
nected between the IREF pin and the adjacent GND
pin is selected to set the reference current to 20 μ A.
The IREF pin is a voltage source at a voltage, V REF ,
of typically 1.2V. The resistor required is therefore
60.4kOhm, which is the standard resistor value that
provides a typical current closest to the 20 μ A target.
Any variation in RREF will affect the internal settings
as described in the section below on RREF selection.
Being a high impedance node, the IREF pin is suscep-
tible to external sources of noise and transients and
should be decoupled with a capacitor across RREF
between the IREF pin and the adjacent GND pin. The
capacitor value should be less than 100pF to avoid
any delay when power is first applied to the A3942
or when coming out of sleep mode. When control-
ling large load currents a larger capacitor may be
required to suppress any transient noise. At power-on
or when coming out of sleep mode this capacitor will
Quad High-Side Gate Driver
for Automotive Applications
be charged at typically 240 μ A until it reaches V REF .
The time taken to charge the capacitor will be approxi-
mately:
t CHARGE = 5 × C
where t CHARGE is in μ s and C is the capacitor value
in nF. At least twice this time should be allowed, after
power-on or after coming out of sleep mode, before
the A3942 is used to switch any loads.
GND Ground All GND pins are internally fused to
the metal die pad to which the chip is soldered. This
allows for high thermal conductance through the GND
pins. Connecting to these pins to a PCB ground plane
improves thermal performance.
Functional Description
Power On When power is applied to either VDD or
VBB, the Output Fault register is initially loaded with
default values, all zeros (0). However, as individual
internal circuits are initially powered on, they may
latch spurious faults in the fault registers for each
channel. Therefore, before operating the A3942 all
fault registers must be cleared by pulsing the RESETZ
pin.
Sleep Mode This mode disables various internal cir-
cuits including the charge pump, VREG, and the logic
circuits. The serial port also is disabled. All Input and
Output Fault register bits are cleared.
To leave sleep mode, pull RESETZ high and then
allow a delay for the charge pump to stabilize. Before
sending commands, clear any spurious faults as
described in the Power On topic.
Faults Faults are categorized either as system faults or
load faults . All faults are ORed to the FAULTZ pin.
System faults are VREG UVLO, CP UVLO, VDD
UVLO, and Thermal Warning. They are not latched in
the channel-specific self-protection circuit fault reg-
isters, however, the flags in the Output Fault register
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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