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参数资料
| 型号： | A3942KLGTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 0K |
| 描述： | IC GATE DVR QUAD HISIDE 38-TSSOP |
| 标准包装： | 8,000 |
| 配置： | 高端 |
| 输入类型： | SPI |
| 延迟时间： | 600ns |
| 电流 - 峰： | 15mA |
| 配置数： | 4 |
| 输出数： | 4 |
| 电源电压： | 4.5 V ~ 60 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
A3942
? Single Fault If there is only one fault detected, the
Output Fault register is filled to indicate that fault.
For a load fault, the Address bits are set to indicate
the affected channel; for example, a short-to-battery
on channel 3 would be written:
10 000 010
On the other hand, for system faults, the Address bits
are irrelevant, and a CP UVLO fault would be loaded
as:
00 010 000
with the Address bits defaulting to 0 0 .
? Multiple System Faults If there are multiple system
faults, the Output Fault register is loaded with the
setting for each system fault (the Address bits re-
main irrelevant, as in the case of a single fault). For
example, when CP UVLO and Thermal Warning
faults both have occurred, the Output Fault register is
loaded with:
00 011 000
? Multiple System Faults and Single Channel Load
Fault If one or more system faults and one or more
load faults from a single channel have occurred, all
faults are loaded into the Output Fault register, with
the channel of the load faults indicated in the Address
bits. For example, a CP UVLO system fault and an
STG load fault on Channel 2 would be written as:
01 010 001
? Multiple Channel Load Faults When load faults
occur on more than one channel, the data cannot be
Quad High-Side Gate Driver
for Automotive Applications
and the second CSZ writes:
11 000 001
In summary, all faults are retrieved by issuing con-
secutive CSZ events until the channel number stops
increasing.
? If there are no faults, this byte will be shifted out
each time:
00 000 000
? If there are only system faults, this byte will be
shifted out each time:
0 0 [1|0] [1|0] [1|0] 0 0 0
? If there are system faults and only one load fault, one
byte contains all of the fault data.
? If there are load faults on more than one channel,
these bytes would be shifted out in succession, and
any existing system faults will be indicated. For ex-
ample, if there were no system faults and load faults
on channels 2, 3, and 4, the following series of bytes
would be shifted out:
0 1 0 0 0 [1|0] [1|0] [1|0]
1 0 0 0 0 [1|0] [1|0] [1|0]
1 1 0 0 0 [1|0] [1|0] [1|0]
0 1 0 0 0 [1|0] [1|0] [1|0]
. . .
Applications
Unused Outputs When any of the four output chan-
nels are not used, the related pins should be connected
as follows:
signalled in a single SDO byte. However, the data
can still be retrieved. The A3942 polls each channel-
specific fault register, in ascending order by channel
number.
Each output is delimited by the appropriate CSZ
event. For example, assume an OL on channel 2 and
Unused Channel Pin
INx
Sx
Dx
Gx
Connection
GND
GND
VBB
Floating
an STG on Channel 4. The first CSZ event writes:
01 000 100
RREF Selection The tolerance on RREF can be
as high as ±4%. Depending on how a specific part
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
15
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相关代理商/技术参数 |
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| A39438-000 | 制造商:TE Connectivity 功能描述:3012-11-230510-CS2324 |
| A3944 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Automotive, Low-Side FET Pre-Driver |
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| A3946GLPTR-T | 制造商:Allegro MicroSystems LLC 功能描述: |
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