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参数资料
| 型号： | A3942KLGTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 11/20页 |
| 文件大小： | 0K |
| 描述： | IC GATE DVR QUAD HISIDE 38-TSSOP |
| 标准包装： | 8,000 |
| 配置： | 高端 |
| 输入类型： | SPI |
| 延迟时间： | 600ns |
| 电流 - 峰： | 15mA |
| 配置数： | 4 |
| 输出数： | 4 |
| 电源电压： | 4.5 V ~ 60 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
D4 Setting
A3942
on a channel-specific basis, according to the following
table:
Handling of
Off-State Faults
0 Registered
1 Ignored
D5 Read Enable Bit This bit enables or disables read-
ing on the serial inputs, according to the following
table:
Quad High-Side Gate Driver
for Automotive Applications
The A3942 enables monitoring for an STG fault after
the MOSFET is turned on and the turn-on blank time,
t ON , expires. (The MOSFET is turned on via the Input
register D0 bit, ORed with the INx discrete input pin
for the channel of the MOSFET, and t ON is set by
Input register D1 and D2 bits). If the MOSFET gate-
to-source voltage exceeds the V DS threshold, then
an STG fault will be registered for that channel, the
MOSFET gate will be discharged, and the FAULTZ
pin will be set low (active).
D5 Setting
0
1
Handling of
Serial Input
Ignored
Registered
An STG fault is latched until cleared (using the Input
register D3 bit). In the meantime, the other channels
can continue to operate normally.
D1 Short to Battery (STB) Fault Bit When a chan-
D6, D7 Address MSB and LSB Bits (Input and Out-
put Fault registers) For channel-specific bits, these
bits are used to specify which channel is indicated.
The channel-specific bits are:
nel turns off, STB fault detection is blanked for t OFF .
Subsequently, if the Sx pin voltage exceeds the V DS
threshold voltage for that channel, an STB fault is
latched. The output for that channel is disabled until
the fault is either cleared (via the Input register D3 bit)
Register
Input
Output
Channel-Specific Bits
D0, D1, D2, D3, D4
D0, D1, D2
or the off-state fault diagnostics are masked (via the
Input register D4 bit).
Because the output is disabled, there is no active
These bits determine the channel, according to the fol-
lowing table:
pull-down during an STB event. Note that, in general,
when the voltage on SX is high enough to trip the STB
comparator, it also trips the OL comparator, and both
D7
0
0
1
1
D6
0
1
0
1
Channel Selected
1
2
3
4
the STB and the OL faults are latched.
D2 Open Load (OL) Fault Bit When a channel turns
off, the OL fault is blanked for t OFF . A small bias
current, I OL , is sourced to the Sx pin of the channel.
There it divides between RSx and the load. If the load
is open, the Sx voltage will rise above the OL fault
Output FAULT Register
D0 Short-to-Ground (STG) Fault Bit The voltage
from drain to source for each MOSFET is monitored.
An internal current source sinks I Dx from the Dx pins
to set the V DS threshold for each channel, the level at
which an STG fault condition is evaluated.
detection threshold. In that case, the output is disabled
until the fault is cleared (via the Input register D3 bit)
or the off-state fault diagnostics are masked (via the
Input register D4 bit).
D3 Thermal Warning Bit A die temperature monitor
is integrated on the A3942 chip. If the die temperature
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A39438-000 | 制造商:TE Connectivity 功能描述:3012-11-230510-CS2324 |
| A3944 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Automotive, Low-Side FET Pre-Driver |
| A3944KLPTR-T | 功能描述:IC PREDRIVER MOSFET 6CH TSSOP RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:5 系列:- 配置:低端 输入类型:非反相 延迟时间:600ns 电流 - 峰:12A 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:- 电源电压:14.2 V ~ 15.8 V 工作温度:-20°C ~ 60°C 安装类型:通孔 封装/外壳:21-SIP 模块 供应商设备封装:模块 包装:散装 配用:BG2A-NF-ND - KIT DEV BOARD FOR IGBT 其它名称:835-1063 |
| A3946 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Half-Bridge Power MOSFET Controller |
| A3946GLPTR-T | 制造商:Allegro MicroSystems LLC 功能描述: |
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