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参数资料
| 型号： | A3942KLGTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 12/20页 |
| 文件大小： | 0K |
| 描述： | IC GATE DVR QUAD HISIDE 38-TSSOP |
| 标准包装： | 8,000 |
| 配置： | 高端 |
| 输入类型： | SPI |
| 延迟时间： | 600ns |
| 电流 - 峰： | 15mA |
| 配置数： | 4 |
| 输出数： | 4 |
| 电源电压： | 4.5 V ~ 60 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
A3942
approaches the maximum allowable level, a thermal
warning signal will be triggered.
Note that this fault sets the FAULTZ pin low (active),
but does not disable the outputs or operation of the
chip.
D4 Charge Pump UVLO Bit The charge pump must
maintain a voltage guard band above V BB , in order
to charge the gates when commanded to turn on the
MOSFETs. If an undervoltage (UVLO) condition is
detected on the charge pump, the FAULTZ pin will be
set low (active), and all outputs will be disabled.
D5 WriteZ (Not Write) Bit In a written byte, D5 = 0.
D6, D7 Address Bits See description, above.
Pin Descriptions
In this section, the functions of the individual termi-
nals of the A3942 are described.
VBB Supply Voltage (Power) The A3942 is fully
operational over the specified range of V BB . The exter-
nal MOSFETs must be supplied by the same voltage
source as the A3942. A bypass capacitor should be
placed as close as practicable to the A3942.
VDD Supply Voltage (Logic) Logic voltage must be
supplied to the A3942. The wide allowable range of
input voltages allows both 3.3 V and 5 V supplies. A
bypass capacitor should be placed as close as practi-
cable to the A3942.
VCP Charge Pump The integrated charge pump is
used to generate a supply above V BB to drive the gates
of the external power MOSFETs. This tripler keeps the
part functional over a wide range of V BB .
CP1 through CP4 Charge Pump Capacitor Con-
nections These are the connections for the two exter-
nal capacitors that level-shift the charge up to V CP .
VREG Internal Linear Voltage Regulator This pro-
vides a connection for an external capacitor that sets
the regulation value for voltage supplied to internal
logic circuits.
Quad High-Side Gate Driver
for Automotive Applications
IN1 through IN4 Discrete Inputs For each output
channel, the gate pin, Gx, sources voltage when the
corresponding INx pin is set high. Gx sinks voltage to
ground when the corresponding INx pin is set low. The
INx setting is logically ORed with the Gate On/Off bit
(Input register bit D0) for the respective output.
D1 through D4 Output Drains For each output chan-
nel, the voltage on the corresponding Dx pin is used
to evaluate STB and STG fault conditions. The A3942
compares the Dx voltage level to the V DS threshold of
the MOSFET to determine if a fault condition exists.
The trip voltage level is set by selecting an appropriate
value for the resistor, RDx, connected to the corre-
sponding current sink. Because both the Dx pins and
RDx are high impedance, each RDx must be placed
as close to the corresponding A3942 Dx pin as practi-
cable.
G1 through G4 Output Gates These pins drive the
gates of the high-side external MOSFETs. They source
voltage from VCP and sink to GND. The correspond-
ing external gate resistors, RGx, should be ≥ 2 k Ω
for consistent switching times between A3942s when
applicable (see I G(HI) and I G(LO) in the Electrical Char-
acteristics table).
If negative voltages are applied, Gx is clamped to
GND by internal diodes. Back-to-back Zener diodes
are internally connected between Gx and Sx.
Sx Output Sources These are used to measure the
source terminal of the external MOSFET. The pins
may be tied directly to the MOSFET. Although the Sx
pins can survive large negative transients, it is recom-
mended to connect a clamp diode between the Sx pin
and ground to limit any negative transients at the Sx
pin when a load is switched off. This helps to avoid
false fault detection caused by transient noise coupling
into adjacent channels which may not be switching
and therefore have no fault blanking during the tran-
sient. This is especially recommended when there is
significant wiring between the load and the Sx pin
even if the load incorporates a recirculation diode.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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| A39438-000 | 制造商:TE Connectivity 功能描述:3012-11-230510-CS2324 |
| A3944 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Automotive, Low-Side FET Pre-Driver |
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