参数资料
型号: A3942KLGTR-T
厂商: Allegro Microsystems Inc
文件页数: 17/20页
文件大小: 0K
描述: IC GATE DVR QUAD HISIDE 38-TSSOP
标准包装: 8,000
配置: 高端
输入类型: SPI
延迟时间: 600ns
电流 - 峰: 15mA
配置数: 4
输出数: 4
电源电压: 4.5 V ~ 60 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 38-TFSOP(0.173",4.40mm 宽)
供应商设备封装: 38-TSSOP
包装: 带卷 (TR)
A3942
That is, the load voltage is within ? V = I D × R D volts
of V BB .
Using V DS = V BB – V L and rearranging, we find that
V DS < I D × R D ± V OS .
Therefore,
R D = ( V DS (trip) ± V OS ) / I D ,
which is also the case for STG faults, described below.
Note that an STB condition generally latches the OL
flag as well.
Under normal conditions R L << RGS and I OL flows
through the load, given
I OL × ( R D + R L ) < V BB – I D × R D ± V OS .
Because I OL × ( R D + R L ) ≈ 0 when the external
MOSFET is off, no fault is registered.
Short-to-Ground Fault Level The effect of the STG
comparator is to compare the external MOSFET V DS
(V L ) to the set trip voltage V BB – I D × R D .
The comparator is active only when the gate is com-
manded on. Also, the sourced current I OL is deacti-
vated.
If V DS is too large, an STG fault is registered when
V L < V BB – I D × R D ± V OS ,
or, because the external MOSFET V DS = V BB – V L ,
V DS > I D × R D ± V OS .
Therefore, the STG trip level in the on state is the
same as the STB level in the off state:
R D = ( V DS (trip) ± V OS ) / I D .
Converse to the preceding, in normal operation
V L > V BB – I D × R D ± V OS ,
or
V DS < I D × R D ± V OS .
Quad High-Side Gate Driver
for Automotive Applications
Power Limits
Power dissipation, P D , is limited by thermal con-
straints. The maximum junction temperature, T J (max),
and the thermal resistance, R θ JA , are given in this
datasheet. The maximum allowed power is then found
for a given ambient, T A , from this equation:
T J = P D × R θ JA + T A , or
P D = ( T J – T A ) / R θ JA .
The three main contributions to power dissipation are:
? quiescent supply, P BB(Q)
? driver outputs, P DRV , and
? logic level supply, P DD .
These three terms appear in the following equation:
P D = P BB(Q) + P DRV + P DD .
The quiescent supply current leads to a baseline power
loss:
P BB(Q) = V BB × I BB(Q) .
In general, the losses in a driver can be quantified as
follows. Given that the driver current leaves Gx to
charge a gate, and assuming that the external circuit
is approximately lossless, then the same charge is
sunk back into Gx. Therefore, all driver current can be
treated as going to heat the chip.
Total current into V BB includes the quiescent current,
I BB(Q) , plus additional current, ? I BB , to energize the
gates. The latter is three times the average gate cur-
rent:
? I BB = 3 × I Gx (av) .
The average load current is calculated using the gate
charge, Q G , from the external MOSFET datasheet and
the switching frequency:
I Gx (av) = f sw × Q G .
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
17
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