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参数资料
| 型号： | A3942KLGTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 14/20页 |
| 文件大小： | 0K |
| 描述： | IC GATE DVR QUAD HISIDE 38-TSSOP |
| 标准包装： | 8,000 |
| 配置： | 高端 |
| 输入类型： | SPI |
| 延迟时间： | 600ns |
| 电流 - 峰： | 15mA |
| 配置数： | 4 |
| 输出数： | 4 |
| 电源电压： | 4.5 V ~ 60 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
A3942
bits D3, D4, and D5, are latched. If the fault condition
is resolved, these flags are latched until they are read,
at which time they are cleared.
Load faults are OL, STB, and STG. They are latched
into the channel-specific self-protection circuit fault
registers, and shifted into Output Fault register bits
D0, D1, and D2 when called. Thus, load faults may be
masked or cleared on a channel-specific basis.
Serial Port Operation
The serial port is compatible with the full duplex
Serial Peripheral Interface (SPI) conventions. The
inputs to the SPI port are logically ORed with the
discrete input pins, INx, settings. This allows indepen-
dent operation using only the discrete inputs, only the
serial inputs, or both. Timing is clocked by an on-
board 4 MHz oscillator.
When a Chip Select event occurs, the Output Fault
register loads one eight-bit byte into the shift register,
and the byte is then shifted out through the SDO pin.
Simultaneously, bits at the SDI pin are shifted into the
shift register (full duplex). At the end of a Chip Select
event, the shift register contents are latched into the
Input register.
Alternative Configurations Multiple A3942s can be
configured together.
? Standalone Connection In this configuration, the
master simultaneously shifts eight bits in through
the SDI pin and shifts eight bits out of the SDO pin.
First, the CSZ pin is set low. Then, the Output Fault
register is loaded with the relevant fault byte (see
the Output Fault Register topic below). Eight clock
cycles are used to perform the shifts.
? Parallel Connection Because each slave has a CSZ
pin, operation is identical to the Standalone configu-
ration. When CSZ is inactive, SDI is “don’t care” and
SDO is high impedance.
Quad High-Side Gate Driver
for Automotive Applications
? Daisy Chain Connection The master shifts n bytes
(eight bits each) during n × 8 clock cycles. Regard-
less of the position of an individual A3942 slave
in the daisy chain, the slaves shift the output byte
during the first eight clock cycles after CSZ goes
low. When CSZ goes high, the eight bits in the Shift
register are latched into the Input register.
Serial Port Disabling Disable the serial port by set-
ting the CSZ pin high while in sleep mode. This loads
the Input register with default values, all zeroes (0).
Serial Port Error Handling Input data is discarded if
the number of bits in an input stream are not a mul-
tiple of eight. Furthermore, unless the number of clock
cycles is a multiple of eight while CSZ is active, any
bits shifted in from the SDI pin are discarded.
Input Register Operation After a valid byte is
latched into the Input register from the shift register,
bit D5 is evaluated to determine if the byte is to be
read. An inactive (0) bit value causes all other bits to
be ignored.
If bit D5 is active (1) the other bits are read and
decoded. Bits D6 and D7 are used to determine which
output channel is updated. Bits D0 through D4 set
the channel-specific operation, including clearing and
masking of faults.
Output Fault Register Operation This register is
loaded with fault data to be shifted out through the
SDO pin. No handshaking is required.
The Output Fault register contains data on active
faults. Four internal channel-specific fault registers
contain any latched fault data for each respective
channel. The following describes how the A3942
determines which channel-specific fault register to
transfer into the Output Fault register.
? No Faults If there are no current faults, the Output
Fault register is loaded with all zeros:
00 000 000
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
14
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