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参数资料
| 型号： | A3942KLGTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | IC GATE DVR QUAD HISIDE 38-TSSOP |
| 标准包装： | 8,000 |
| 配置： | 高端 |
| 输入类型： | SPI |
| 延迟时间： | 600ns |
| 电流 - 峰： | 15mA |
| 配置数： | 4 |
| 输出数： | 4 |
| 电源电压： | 4.5 V ~ 60 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 38-TSSOP |
| 包装： | 带卷 (TR) |
A3942
If all four outputs are supplying this current,
Quad High-Side Gate Driver
for Automotive Applications
? Use both bulk storage capacitors (for example, elec-
and
? I BB = 4 (3 × I Gx ) = 12 × f SW × Q G ,
trolytic) and low impedance bypass capacitors (for
example, ceramic) on all supply pins. See the Func-
tional Block Diagram for recommended values.
P DRV = V BB × ? I BB = 12 × f SW × Q G × V BB .
Finally, loss in the logic circuits is
P DD = V DD × I DD .
Example :
Find the junction temperature with one IRFZ44ES
MOSFET at each output, being switched at 5 kHz, and
given V BB = 14 V and V DD = 5.5 V.
Answer: The IRFZ44ES datasheet gives Q G (max)
= 60 nC (note that this parameter depends on circuit
design constraints, such as V DS ). The Electrical Char-
acteristics table gives the following maximum values
for the A3942: I BB(Q) = 10 mA, V DD = 5.5 V, and I DD
= 3 mA.
First, calculate total power loss:
P D = V BB I BB(Q) + 12 f sw Q G V BB + V DD I DD
= 14 V × 11 mA
+ 4 × 3 × 5 kHz ×60 nC × 14 V
+ 5.5 V × 3 mA
= 221 mW .
Then, the junction temperature can be found for a
given ambient temperature; T A = 125°C is assumed
here. Thermal resistance depends significantly on the
board design; R θ JA = 100 °C/W is assumed here. Sub-
stituting these values:
T J = P D × R θ JA + T A
= 221 mW × 100 °C/W + 125°C
= 147°C .
LAYOUT AND COMPONENTS
General good practices should be followed. In addi-
tion, the following are recommended:
? Locate bypass capacitors (VBB, VDD, VREG, and
IREF) as close to the A3942 as practicable.
? Traces to bypass capacitors should be as wide as
practicable; minimize the number of vias.
? Input and output lines should not be in close proxim-
ity. If they do overlap, it should be at right angles.
? Use ample copper in the ground and power paths.
Use planes or fills where possible.
? The A3942 ground and VBB supply should be star-
connected to the power ground and supply.
? The trace connecting the RDx resistors to the A3942
Dx pins should be as short as possible.
? The trace leaving the other side of the RDx resistors
can be long because it has a low impedance path to
ground; however, it must run independently to the re-
spective external MOSFET in order to make a Kelvin
connection.
? All support capacitors are to be referenced to the
A3942 ground plane or ground fill. Minimize loop
area of traces.
? These traces should be as wide as practicable: VBB,
VDD, VREG, VCP, and Gx. Secondarily, it is also
preferred that the traces to the charge pump caps be
as wide as practicable. In both cases, the number of
vias should be minimized.
? Minimize the distance connecting to ground pins in
order to minimize ground loops.
Finally, a note about thermals. Because the A3942
ground pins are internally fused to the die mounting
pad, they are the main path for heat dissipation. In
applications producing high junction temperatures,
care must be given to designing the thermal path. For
example, multiple thermal vias should be run from
ground pins down to the ground plane. If space allows,
wide traces from ground pins to exposed copper fills
on the top layer efficiently release heat through con-
vection cooling.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
18
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| A3944 | 制造商:ALLEGRO 制造商全称:Allegro MicroSystems 功能描述:Automotive, Low-Side FET Pre-Driver |
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