参数资料
型号: A4935KJPTR-T
厂商: Allegro Microsystems Inc
文件页数: 10/25页
文件大小: 0K
描述: IC MOSFET DVR AUTO 3PH 48-LQFP
标准包装: 1
配置: 3 相桥
输入类型: PWM
延迟时间: 90ns
配置数: 1
输出数: 3
电源电压: 5.5 V ~ 50 V
工作温度: -40°C ~ 150°C
安装类型: 表面贴装
封装/外壳: 48-LQFP 裸露焊盘
供应商设备封装: 48-LQFP 裸露焊盘(7x7)
包装: 标准包装
产品目录页面: 1141 (CN2011-ZH PDF)
其它名称: 620-1300-6
A4935
Automotive 3-Phase MOSFET Driver
? Setting PWML low turns off active low-side drives and turns on
the complementary high-side drives. This provides low-side–
chopped slow-decay PWM with synchronous rectification.
? PWMH and PWML may also be connected together and driven
with a single PWM signal. This provides fast-decay PWM with
synchronous rectification.
COAST Pin An active-low input, which forces low all gate drive
outputs, GHx and GLx, and turns off all external FETs. This can
be used to protect the FETs and the motor in the case of a short
circuit. Using COAST does not clear any faults, so the fault flags
can still be decoded and the fault register data word can be read.
Because COAST turns off all the external FETs, it can also be used
to provide fast-decay PWM without synchronous rectification.
RESET Pin This is an active-low input, and when active it
allows the A4935 to enter sleep mode. When RESET is held low
for longer than the reset pulse time, t RES , the regulator and all
internal circuitry are disabled and the A4935 enters sleep mode.
During sleep mode, current consumption from the VBB and VDD
supplies is reduced to a minimal level. In addition, latched faults
and the corresponding fault flags are cleared. When the A4935 is
coming out of sleep mode, the protection logic ensures that the
gate drive outputs are off until the charge pump reaches its
Table 1. Phase Control Truth Table
correct operating condition. The charge pump stabilizes in
approximately 3 ms under nominal conditions.
RESET can be used also to clear latched fault flags without
entering sleep mode. To do so, hold RESET low for less then the
reset pulse time, t RES . This clears any latched fault that disables
the outputs, such as short circuit detection or bootstrap capacitor
undervoltage, and also clears the fault register.
Note that the A4935 can be configured to start without any exter-
nal logic input. To do so, pull up the RESET pin to V BB by means
of an external resistor. The resistor value should be between
20 and 33 k Ω .
CCEN Pin This input provides an override to allow both the high-
side and the low-side external FETs of any phase to be active at
the same time, enabling cross-conduction. As an extra level of
safety, cross-conduction can only occur when RDEAD is tied to
AGND and CCEN is set high. If the CCEN input is inadvertently
disconnected from the controller, an internal pull-down resistor
ensures that the outputs revert to a safe condition.
ESF Pin This is the Enable Stop on Fault input. It determines the
action that is taken when certain faults are detected. See the Fault
Protection and Diagnostics section for details.
RDEAD
RESET
CCEN
Inputs
COAST PWMH
PWML
xHI
xLO
GHx
Outputs
GLx
Sx
Comment
x
x
x
>0.2 V
x
x
x
x
x
x
AGND
AGND
x
x
AGND
AGND
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
x
x
x
x
x
x
x
x
x
x
x
x
x
x
0
1
x
1
1
x
1
1
1
1
1
1
1
1
x
0
1
1
x
1
1
x
0
0
1
1
0
0
1
0
x
x
1
1
x
1
1
x
1
1
0
0
0
0
0
1
x
x
1
1
0
0
1
1
0
1
0
1
0
1
1
1
x
x
1
1
0
1
0
1
1
0
1
0
1
0
1
1
x
x
1
1
L
L
H
L
L
L
H
H
H
L
H
L
Z
L
L
H
L
H
L
L
H
H
L
L
L
H
L
H
Z
L
L
H
Z
LS
HS
Z
LS
LS
HS
HS
HS
LS
HS
LS
Z
Z
Z
U
Phase disabled
Phase sinking
Phase sourcing
Phase disabled
Sink; high-side PWM on other phases
Slow decay, SR; low-side recirculation
Slow decay, SR; high-side recirculation
Source; low-side PWM on other phases
Fast decay, SR
Fast decay, SR
Slow decay, SR; high-side recirculation
Slow decay, SR; low-side recirculation
Low power shutdown
Coast
Phase disabled
Cross-conduction
x = don’t care, HS = high-side FET active, LS = low-side FET active, Z = high impedance, both FETs off, U = undefined, SR = synchronous rectification
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
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