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| 型号： | A4935KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 12/25页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DVR AUTO 3PH 48-LQFP |
| 标准包装： | 1 |
| 配置： | 3 相桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 3 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP 裸露焊盘 |
| 供应商设备封装： | 48-LQFP 裸露焊盘（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1300-6 |
A4935
Automotive 3-Phase MOSFET Driver
switching. Any short faults detected will always be latched in the
fault register.
When a short or undervoltage fault is present, a clock can be
applied to FF2 and detailed fault information can be read from
FF1 as a serial word. This can be used to determine on which of
the six external FETs a short is being detected, or which of the
monitored voltages have gone below their undervoltage threshold
level. Fault register serial access operation is detailed in the Fault
Register Serial Access section.
Fault States
Overtemperature If the junction temperature exceeds the over-
temperature threshold, typically 165°C, the A4935 will enter the
overtemperature fault state and FF1 will go high. The overtem-
perature fault state, and FF1, will only be cleared when the tem-
perature drops below the recovery level defined by T JF – T JFhys .
Note that an overtemperature fault does not permit access to the
fault register because FF2 is pulled low.
If ESF is set high when an overtemperature is detected, the out-
puts will be disabled automatically while the fault state is present.
If ESF is set low, then no circuitry will be disabled. In this case
external control circuits must take action to limit the power dis-
sipation in some way so as to prevent overtemperature damage to
the chip and unpredictable device operation.
VREG Undervoltage VREG supplies the low-side gate driver
and the bootstrap charge current. It is critical to ensure that the
voltages are sufficiently high before enabling any of the outputs.
If the voltage at VREG, V REG , drops below the falling VREG
undervoltage lockout threshold, V REGUVoff , then the A4935 will
enter the VREG undervoltage fault state. In this fault state, both
FF1 and FF2 will be high, and the outputs will be disabled. The
VREG undervoltage fault state and the fault flags will be cleared
when V REG rises above the rising VREG undervoltage lockout
threshold, V REGUVon .
The VREG undervoltage monitor circuit is active during pow-
er-up, and the A4935 remains in the VREG undervoltage fault
state until V REG is greater than the rising VREG undervoltage
lockout threshold, V REGUVon .
Any time the A4935 enters the VREG undervoltage fault state,
bit 7 in the fault register will be set and will remain set until cleared
by a register reset (see the Fault Register Serial Access section).
Bootstrap Capacitor Undervoltage The A4935 monitors the
voltage across the individual bootstrap capacitors to ensure they
have sufficient charge to supply the current pulse for the high-
side drive. Before a high-side drive can be turned on, the voltage
across the associated bootstrap capacitor must be higher than the
turn-on voltage limit. If this is not the case, then the A4935 will
start a bootstrap charge cycle by activating the complementary
low-side drive. Under normal circumstances, this will charge the
bootstrap capacitor above the turn-on voltage in a few microsec-
onds and the high-side drive will then be enabled.
The bootstrap voltage monitor remains active while the high-side
drive is active and if the voltage drops below the turn-off voltage
a charge cycle is initiated.
In either case, if there is a fault that prevents the bootstrap capaci-
tor charging, then the charge cycle will timeout, the fault flags
(indicating an undervoltage) will be set, and the outputs will be
disabled. In addition, the appropriate bit in the fault register will
be set. This allows the specific phase giving the bootstrap under-
voltage to be determined by reading the serial data word.
The bootstrap undervoltage fault state remains latched until
RESET is set low or a serial read of the fault register is com-
pleted.
VDD Undervoltage The logic supply voltage at VDD is moni-
tored to ensure correct logical operation. If an undervoltage
on VDD is detected, the outputs will be disabled. In addition,
because the state of other reported faults cannot be guaranteed,
all fault states, fault flags, and the fault register are reset and
replaced by the fault flags corresponding to a VDD undervoltage
fault state. For example, a VDD undervoltage will reset an exist-
ing short circuit fault condition and replace it with a VDD under-
voltage fault. When the VDD undervoltage condition is removed,
all flags will be cleared and the outputs enabled.
Short Fault Operation Shorts in the power bridge are determined
by monitoring the drain-souce voltage, V DS , of each active FET
and comparing it to the fault threshold voltage at the VDSTH pin.
Because power MOSFETs take a finite time to reach the rated on-
resistance, the measured drain-source voltages will show a fault
as the phase switches. To avoid such false short fault detections,
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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