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| 型号： | A4935KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 16/25页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DVR AUTO 3PH 48-LQFP |
| 标准包装： | 1 |
| 配置： | 3 相桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 3 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP 裸露焊盘 |
| 供应商设备封装： | 48-LQFP 裸露焊盘（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1300-6 |
A4935
Automotive 3-Phase MOSFET Driver
Applications Information
Power Bridge Management Using PWM Control
The A4935 provides individual high-side and low-side controls
for each phase, plus two PWM control signals and a coast con-
trol. This allows a wide variety of 3-phase bridge control schemes
to be implemented.
A
B
C
A
B
C
For advanced schemes using sinusoidal current control, each FET
in the 3-phase bridge can be controlled individually without using
the PWM and COAST inputs. This requires a higher perfor-
mance external controller, with a PWM output for each phase. If
full external control over dead time is required, then six PWM
outputs will be required, one for each FET in the bridge. In this
type of system, the external controller has full control over the
current-decay method, load current recirculation paths, braking,
and coasting.
Figure 2A shows an example of the paths of the bridge and load
currents when each phase is controlled directly. The PWM inputs
PWMH and PWML are both tied high and COAST is tied high.
Drive Recirculate
Phase A B C Phase A B C
xHI 1 1 0 xHI 0 0 0
xLO 0 0 1 xLO 1 1 1
GHx H H L GHx L L L
GLx L L H GLx H H H
(A) Slow decay, synchronous rectification, high-side PWM using phase inputs
In this case the high-side FETs are switched off during the current
decay time (PWM off-time) and load current recirculates through
A
B
C
A
B
C
the low-side FETs. This is commonly referred to as high-side
chopping or high-side PWM. During the PWM off-time, the
complementary FETs are turned on, to short the body diode and
provide synchronous rectification.
Figure 2A shows one combination of phase states, and the same
principal applies to any of the possible phase states. This princi-
Phase
xHI
xLO
GHx
GLx
Drive
A B
1 1
0 0
H H
L L
C
0
1
L
H
Recirculate
Phase A B
xHI 1 1
xLO 0 0
GHx H H
GLx L L
C
1
0
H
L
pal also applies when the low-side FETs are turned off during the
PWM off-time and the load current recirculates through the high
side FETs, as shown in figure 2B.
For less complex control schemes, for example where simple
block commutation is used, it is possible to control the bridge
with three logic signals (one for each phase) and a single PWM
(B) Slow decay, synchronous rectification, low-side PWM using phase inputs
signal. Figure 2C shows an example of 2-phase excitation with
A
B
C
A
B
C
high-side PWM, as commonly used in a block commutation
scheme. The PWMH input is used to modulate the phase currents
and PWML is held high. During the PWM off-time, the active
high-side FET is turned off and the complementary low-side FET
is turned on. Note that the phase control signals in this case do
not change and all PWM switching, for any phase combination, is
managed by a single PWM signal. For low-side PWM, PWMH is
held high and the PWM signal is applied to PWML.
By tying PWMH and PWML together and applying a PWM
signal to them, the load current can be controlled using fast decay
by effectively reversing the supply polarity. This feature operates
Drive Recirculate
Phase A B C Phase A B C
xHI 1 0 0 xHI 1 0 0
xLO 0 0 1 xLO 0 0 1
GHx H L L GHx L L L
GLx L L H GLx H L H
PWMH 1 PWMH 0
PWML 1 PWML 1
(C) Slow decay, synchronous rectification, high-side PWM using PWMx inputs
Figure 2. Power bridge current paths
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
16
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