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| 型号： | A4935KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 6/25页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DVR AUTO 3PH 48-LQFP |
| 标准包装： | 1 |
| 配置： | 3 相桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 3 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP 裸露焊盘 |
| 供应商设备封装： | 48-LQFP 裸露焊盘（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1300-6 |
A4935
Automotive 3-Phase MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued) valid at T J = –40°C to 150°C, V DD = 3 to 5.5 V, V BB = 7 to 50 V,
unless noted otherwise
Characteristics
Small Signal –3 dB Frequency Bandwidth
Settling Time
Output Dynamic Range
Output Current Sink
Output Current Source
VREG Supply Ripple Rejection
DC Common Mode Rejection
AC Common Mode Rejection
Common Mode Recovery Time
Output Slew Rate
Input Overload Recovery
Symbol
BW G
t SETTLE
V CSOUT
I CSsink
I CSsource
PSRR
CMRR
CMRR
t CMrec
SR
t IDrec
Test Conditions
V ID = 10 mV pp , G = 5 V/V
To within 10% of steady state,
V CSOUT = 1 Vpp square wave
–100 μ A < I CSOUT < 100 μ A
V ID = –400 mV, V CSOUT = 1.5 V
V ID = 400 mV, V CSOUT = 1.5 V
CSP = CSN = AGND, 0 to 300 kHz
CSP = CSN = 0 to 200 mV step
V CM = 200 mVpp, 0 to 1 MHz
To within 100 mV of steady state,
V CM = +4 V step within CMR
10% to 90%, V ID = 0 to 175 mV step
To within 10% of steady state,
V ID = 250 mV to 0 V step
Min.
–
–
0.1
1
–
–
–
–
–
–
–
Typ.
1.6
400
–
–
–
45
38
28
1
20
500
Max.
–
–
V DD
– 0.3
–
–1
–
–
–
–
–
–
Units
MHz
ns
V
mA
mA
dB
dB
dB
μ s
V/ μ s
ns
Protection
VREG Undervoltage Lockout Threshold
Bootstrap Undervoltage Threshold
Bootstrap Undervoltage Hysteresis
VDD Undervoltage Turn-Off Threshold
VDD Undervoltage Hysteresis
VDSTH Input Range
VDSTH Input Current
VDRAIN Input Voltage
VDRAIN Input Current
Short-to-Ground Threshold Offset 5
Short-to-Battery Threshold Offset 6
Overtemperature Fault Flag Threshold
Overtemperature Fault Hysteresis
V REGUVon
V REGUVoff
V BOOTUV
V BOOTUVhys
V DDUV
V DDUVhys
V DSTH
I DSTH
V DRAIN
I DRAIN
V STGO
V STBO
T JF
T JFhys
V REG rising
V REG falling
Cx with respect to Sx
V DD falling
0 V < V DSTH < 2 V
V DSTH = 2 V,
V BB = 12 V, 0 V < V DRAIN < V BB
High-side on, V DSTH ≥ 1 V
High-side on, V DSTH < 1 V
Low-side on, V DSTH ≥ 1 V
Low-side on, V DSTH < 1 V
Temperature increasing
Recovery = T JF – T JFhys
7.5
6.75
59
–
2.45
50
0.1
–30
7
–
–150
–150
– 150
–150
150
–
8
7.25
–
13
2.7
100
–
–10
V BB
–
±100
±50
±100
±50
170
15
8.5
7.75
69
–
2.85
150
2
–
50
250
+150
+150
+150
+150
–
–
V
V
%V REG
%V REG
V
mV
V
μ A
V
μ A
mV
mV
mV
mV
oC
oC
1 Functions
correctly, but parameters are not guaranteed, below the general limits (7 V).
2 See Gate Drive Timing diagrams.
3 For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
4 See Fault Output Timing diagram.
5 As V Sx decreases, fault occurs if V BAT –V Sx > V STG . STG threshold, V STG = V DSTH + V STGO .
6 As V Sx increases, fault occurs if V Sx – V LSS > V STB . STB threshold, V STB = V DSTH +V STBO .
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
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