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| 型号： | A4935KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 8/25页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DVR AUTO 3PH 48-LQFP |
| 标准包装： | 1 |
| 配置： | 3 相桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 3 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP 裸露焊盘 |
| 供应商设备封装： | 48-LQFP 裸露焊盘（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1300-6 |
A4935
Automotive 3-Phase MOSFET Driver
Functional Description
The A4935 is a three-phase MOSFET driver (pre-driver) with
separate supplies for the logic, and for the analog and drive sec-
tions. This permits operation with a regulated logic supply from
3 to 5.5 V and with an unregulated main supply of 7 to 50 V.
The six high current gate drives are capable of driving a wide
range of N-channel power MOSFETs, and are configured as three
high-side drives and three low-side drives. Each drive can be con-
trolled with a logic level input compatible with 3.3 or 5 V logic.
The A4935 provides all the necessary circuits to ensure that the
gate-source voltage of both high-side and low-side external FETs
are above 10 V, at supply voltages down to 7 V. For extreme
battery voltage drop conditions, correct functional operation is
guaranteed at supply voltages down to 5.5 V, but with a reduced
gate drive voltage.
The control inputs to the A4935 provide a very flexible solution
for many motor control applications. For full sinusoidal excita-
tion, each phase can be driven with an independent PWM signal.
For less complex drive solutions, the two PWM inputs, PWML
and PWMH, allow simple high-side, low-side, or fast-decay con-
trol with a single PWM signal.
A current sense amplifier allows motor current to be sensed by a
low-value sense resistor in the ground connection to the power
bridge.
The A4935 includes a number of protection features against
undervoltage, overtemperature, and power bridge faults. Fault
states enable responses by the device or by the external controller,
depending on the fault condition and logic settings. Two fault flag
outputs, FF1 and FF2, are provided to signal detected faults to an
external controller. Diagnostics include an internal fault register,
which can be accessed by serial read out using the fault flag pins.
Power Supplies
Two power supply voltages are required, one for the logic
interface and one for the analog and output drive sections. Both
supplies should be decoupled with ceramic capacitors connected
close to the supply and ground pins.
The logic supply, connected to VDD, allows the flexibility of a
3.3 or 5 V logic interface. The main power supply should be con-
nected to VBB through a reverse voltage protection circuit. The
A4935 operates within specified parameters with a VBB supply
from 7 to 50 V and functions correctly with a supply down to
5.5 V. This provides a very rugged solution for use in the harsh
automotive environment.
Gate Drives
The A4935 is designed to drive external, low on-resistance,
power N-channel MOSFETs. It supplies the large transient cur-
rents necessary to quickly charge and discharge the external FET
gate capacitance in order to reduce dissipation in the external
FET during switching. The charge and discharge rate can be
controlled using an external resistor in series with the connection
to the gate of the FET.
Gate Drive Voltage Regulation The gate drives are powered
by an internal regulator which limits the supply to the drives
and therefore the maximum gate voltage. When the V BB supply
greater than about 16 V, the regulator is a simple linear regulator.
Below 16 V, the regulated supply is maintained by a charge pump
boost converter, which requires a pump capacitor connected
between the CP1 and CP2 pins. This capacitor must have a mini-
mum value of 220 nF, and is typically 470 nF.
The regulated voltage, nominally 13 V, is available on the VREG
pin. A sufficiently large storage capacitor must be connected to
this pin to provide the transient charging current to the low-side
drives and the bootstrap capacitors.
Top-off Charge Pump An additional top-off charge pump is
provided for each phase. The charge pumps allow the high-side
drives to maintain the gate voltage on the external FETs indefi-
nitely, ensuring so-called 100% PWM if required. This is a low
current trickle charge pump, and is operated only after a high-side
FET has been signaled to turn on. The floating high-side gate
drive requires a small bias current (<20 μ A) to maintain the high-
level output. Without the top-off charge pump, this bias current
would be drawn from the bootstrap capacitor through the Cx pin.
The charge pump provides sufficient current to ensure that the
bootstrap voltage and thereby the gate-source voltage is main-
tained at the necessary level.
Note that the charge required for initial turn-on of the high-side
gate is always supplied by the bootstrap capacitor. If the bootstrap
capacitor becomes discharged, the top-off charge pump will not
provide sufficient current to allow the FET to turn on.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
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