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| 型号： | A4935KJPTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 11/25页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DVR AUTO 3PH 48-LQFP |
| 标准包装： | 1 |
| 配置： | 3 相桥 |
| 输入类型： | PWM |
| 延迟时间： | 90ns |
| 配置数： | 1 |
| 输出数： | 3 |
| 电源电压： | 5.5 V ~ 50 V |
| 工作温度： | -40°C ~ 150°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP 裸露焊盘 |
| 供应商设备封装： | 48-LQFP 裸露焊盘（7x7） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1300-6 |
A4935
Current Sense Amplifier
Automotive 3-Phase MOSFET Driver
damage to components, the external controller can take low the
An uncommitted differential sense amplifier is provided to allow
the use of either low value sense resistors or a current shunt as the
current sensing element. The input common mode range, CMR,
allows the below-ground current sensing typically required in
PWM motor control during switching transients.
Input is on the CSN and CSP pins. The output of the sense ampli-
fier is available at CSOUT and can be used in a peak current
control system.
The gain of the sense amplifier is set using external input and
feedback resistors. The gain must be set to be greater than the
specified minimum to ensure stability. Typically the gain will be
set between 5 and 50 V/V. Output offset can also be added using
external resistors. Examples of setting the sense amplifier gain
and offset are provided in the Applications Information section.
Diagnostics
Several diagnostic features are integrated into the A4935 to
provide indication of fault conditions and, if required, take action
to prevent permanent damage. In addition to system wide faults
such as undervoltage and overtemperature, the A4935 integrates
individual drain-source monitors for each external FET, to pro-
COAST input or all of the xHi and xLO phase control inputs.
VDSTH Pin Faults on the external FETs are determined by
measuring the drain-source voltage, V DS , of each active FET
and comparing it to the threshold voltage applied to the VDSTH
input, V DSTH . To avoid false fault detection during switching tran-
sients, the comparison is delayed by an internal blanking timer.
VDRAIN This is a low-current sense input from the top of the
external FET bridge. This input allows accurate measurement of
the voltage at the drain of the high-side FETs. It should be con-
nected directly to the common connection point for the drains of
the power bridge FETs at the positive supply connection point.
The input current to the VDRAIN pin is proportional to the volt-
age on the VDSTH pin and can be approximated by:
I VDRAIN = 72 × V DSTH + 52 ,
where I VDRAIN is the current into the VDRAIN pin, in μ A, and
V DSTH is the voltage on the VDSTH pin, in V.
FF1 and FF2 Pins are open drain output fault flags, which
indicate fault conditions by their state, as shown in table 2. In
the event that two or more faults are detected simultaneously, the
state of the fault flags will be determined by a logical OR of the
flag states for all detected faults.
vide short circuit detection. When a short or undervoltage fault
is being reported, detailed fault information can be read from the
fault outputs as a serial data word.
Table 2. Fault Definitions
Flag State
Fault Description
FF1 FF2
Disable Outputs*
ESF ESF
Low High
Flag
Latched
Diagnostic Management Pins
ESF Pin This pin (Enable Stop on Fault) determines the action
taken when a short circuit or overtemperature fault is detected. It
does not affect undervoltage fault condition actions.
When ESF is set to logic high, any short circuit or overtem-
perature fault condition will pull all the gate drive outputs low
and coast the motor. For short faults, this disabled state will be
latched until RESET goes low or a serial read is completed.
0
0
0
0
1
1
1
1
0
1
1
1
0
1
1
1
No fault
Short-to-ground
Short-to-supply
Shorted load
Overtemperature
VDD undervoltage
VREG undervoltage
Bootstrap undervoltage
No
No
No
No
No
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
–
If ESF high
If ESF high
If ESF high
No
No
No
Yes
When ESF is set to logic low, under most conditions the A4935
will not disrupt normal operation and therefore will not protect
the drive circuit or motor from damage. This is the case even
though the fault flags are set. This allows the actions taken to be
controlled externally by the system control circuits. To prevent
* Yes indicates all gate drives low, and all FETs off.
When ESF is high, short faults will always cause the fault flags
to be latched. When ESF is low, a short fault will only be flagged
when the fault is present, and the flag state will not be latched.
This provides additional diagnostics flexibility during FET
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
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