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参数资料
| 型号： | AD6654CBCZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 40/88页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT W/4CH RSP 256CSPBGA |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 92.16M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 电压电源： | 模拟和数字 |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA，CSPBGA |
| 供应商设备封装： | 256-CSPBGA（17x17） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
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AD6654
Rev. 0 | Page 45 of 88
CHANNEL RAM COEFFICIENT FILTER (CRCF)
Following the DRCF is the programmable decimating CRCF
FIR filter. The only difference between the DRCF and CRCF
filters is the coefficient bit width. The DRCF has 14-bit
coefficients, while the CRCF has 20-bit coefficients.
This filter can calculate up to 64 asymmetrical filter taps or up
to 128 symmetrical filter taps. The filter is capable of a
programmable decimation rate from 1 to 16. The flexible
coefficient offset feature allows loading multiple filters into the
coefficient RAM and changing the filters on the fly. The
decimation phase feature allows for a polyphase implementa-
tion in which multiple AD6654 channels are used to process a
single carrier.
The CRCF filter has 20-bit input and output data and 20-bit
coefficient data. The number of filter taps to calculate is
programmable and is set in the CRCF taps register. The value
of the number of taps minus one is written to this register. For
example, a value of 19 in the register corresponds to 20 filter
taps. The decimation rate is programmable using the 4-bit
CRCF decimation rate word in the CRCF control register.
Again, the value written is the decimation rate minus one.
BYPASS
The CRCF filter can be used in normal operation or bypassed
using the CRCF bypass bit in the CRCF control register. When
the CRCF filter is bypassed, no scaling is applied and the output
of the filter is the same as the input to the CRCF filter.
SCALING
The output of the CRCF filter can be scaled using the 2-bit
CRCF scaling word in the CRCF control register. Table 22
shows the valid values for the 2-bit word and the corresponding
settings. | ∑COEFF | is the sum of all coefficients (in normalized
form) used to calculate the FIR filter.
Table 22. CRCF Scaling Factor Settings
CRCF Scale Word[1:0]
Scaling Factor
00
18.06 dB attenuation
01
12.04 dB attenuation
10
6.02 dB attenuation
11
No scaling, 0 dB
SYMMETRY
The CRCF filter does not require symmetrical filters. However,
if the filter is symmetrical, then the symmetry bit in the CRCF
control register should be set. When this bit is set, only half the
impulse response needs to be programmed into the CRCF
coefficient memory registers. For example, if the number of
filter taps is equal to 15 or 16 and the filter is symmetric, then
only eight coefficients need to be written into the coefficient
memory.
Because a total of 64 taps can be written into the memory
registers, the CRCF can perform 64 asymmetrical filter taps or
128 symmetrical filter taps.
COEFFICIENT OFFSET
More than one set of filter coefficients can be loaded into the
coefficient RAM at any time (given sufficient RAM space). The
coefficient offset can be used in this case to access the two or
more different filters. By changing the coefficient offset, the
filter coefficients being accessed can be changed on the fly.
This decimal offset value is programmed in the CRCF
coefficient offset register. When this value is changed during
the calculation of a particular output data sample, the sample
calculation is completed using the old coefficients and the new
coefficient offset is brought into effect from the next data
sample calculation.
DECIMATION PHASE
When more than one channel of the AD6654 is used to process
one carrier, polyphase implementation of the corresponding
channels’ DRCF or CRCF is possible using the decimation
phase feature. This feature can be used only under certain
conditions. The decimation phase is programmed using the
4-bit CRCF decimation phase word of the CRCF control
register.
MAXIMUM NUMBER OF TAPS CALCULATED
The output rate of the CRCF filter is given by
CRCF
DRCF
CRCF
M
f
=
where:
fDRCF
is the data rate out of the DRCF filter and into the CRCF
filter.
MCRCF
is the decimation rate in the CRCF filter.
The CRCF filter consists of two multipliers (one each for the
I and Q paths). Each multiplier, working at the high speed clock
rate (PLL clock), can multiply (or tap once). Therefore, the
maximum number of filter taps that can be calculated
(symmetrical or asymmetrical filter) is given by
Maximum Number of Taps
= ceil
CRCF
PLLCLK
f
1
fPLLCLK
is the high speed internal processing clock generated by
the PLL clock multiplier.
fCRCF
is the output rate of the CRCF filter as previously
calculated.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全称:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-125EBZ | 功能描述:BOARD EVAL W/AD6655 & SOFTWARE RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
| AD6655-125EBZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-150EBZ | 功能描述:BOARD EVAL FOR 150MSPS AD6655 RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
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