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| 型号： | AD6654CBCZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 79/88页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT W/4CH RSP 256CSPBGA |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 92.16M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 电压电源： | 模拟和数字 |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA，CSPBGA |
| 供应商设备封装： | 256-CSPBGA（17x17） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
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AD6654
Rev. 0 | Page 80 of 88
Table 37. DRCF Multiply Accumulate Scale Bits
DRCF Scale <1:0>
Scale Factor
00
18.06 dB attenuation (left-shift 3 bits)
01
12.04 dB attenuation (left-shift 2 bits)
10
6.02 dB attenuation (left-shift 1 bit)
11
No scaling (0 dB)
<7:4>: DRCF Decimation Rate. This 4-bit word should be
written with one less than the decimation rate of the DRCF
filter. A value of 0 represents a decimation rate of 1 (no rate
change), and the maximum value of 15 represents a decimation
of 16. Filtering can be implemented regardless of the
decimation rate.
<3:0>: DRCF Decimation Phase Bits. This 4-bit word represents
the decimation phase used by the DRCF filter. The valid range
is 0 up to MDRCF 1, where MDRCF is the decimation rate of the
DRCF filter. This word is primarily used for synchronization of
multiple channels of the AD6654, when more than one channel
is used for filtering one signal (one carrier).
DRCF Coefficient Offset <7:0>
This register is used to specify which section of the 64-word
coefficient memory is used for a filter. It can be used to select
between multiple filters that are loaded into memory and
referenced by this pointer. This register is shadowed, and the
filter pointer is updated every time a new filter is started. This
allows the coefficient offset to be written even while a filter is
being computed without disturbing operation. The next sample
comes out of the DRCF with the new filter.
DRCF Taps <6:0>
This register is written with one less than the number of taps
that are calculated by the DRCF filter. The filter length is given
by the decimal value of this register plus 1. A value of 0
represents a 1-tap filter, and a value of 0x28 (40 decimal)
represents a 41-tap filter.
DRCF Start Address <5:0>
This register is written with the starting address of the DRCF
coefficient memory to be updated.
DRCF Final Address <5:0>
This register is written with the ending address of the DRCF
coefficient memory to be updated.
DRCF Coefficient Memory <13:0>
DRCF Memory. This memory consists of 64 words, and each
word is 14 bits wide. The data written to this memory space is
expected to be 14-bit, twos complement format. See the
Decimating RAM Coefficient Filter (DRCF) section for the
method to program the coefficients into the coefficient
memory.
CRCF Control Register <11:0>
<11>: CRCF Bypass Bit. When this bit is set, the DRCF filter is
bypassed and, therefore, its output is the same as its input.
When this bit is cleared, the CRCF has normal operation as
programmed by its control register.
<10>: Symmetry Bit. When this bit is set, it indicates that the
CRCF is implementing a symmetrical filter and only half the
impulse response needs to be written into the CRCF coefficient
RAM. When this bit is cleared, the filter is asymmetrical and
the complete impulse response of the filter should be written
into the coefficient RAM. When this filter is symmetrical, it can
implement up to 128 filter taps.
<9:8>: CRCF Multiply Accumulate Scale Bits. The output of the
CRCF filter is scaled according to the value of these bits.
Table 38 lists the attenuation corresponding to each setting.
Table 38. CRCF Multiply Accumulate Scale Bits
CRCF Scale<1:0>
Scale Factor
00
18.06 dB attenuation (left-shift 3 bits)
01
12.04 dB attenuation (left-shift 2 bits)
10
6.02 dB attenuation (left-shift 1 bit)
11
No scaling (0 dB)
<7:4>: CRCF Decimation Rate. This 4-bit word should be writ-
ten with one less than the decimation rate of the CRCF filter. A
value of 0 represents a decimation rate of 1 (no rate change) and
the maximum value of 15 represents a decimation of 16.
Filtering operation is done regardless of the decimation rate.
<3:0>: CRCF Decimation Phase. This 4-bit word represents the
decimation phase used by the CRCF filter. The valid range is 0
to MCRCF 1, where MCRCF is the decimation rate of the
CRCF filter. This word is primarily used for synchronization of
multiple channels of the AD6654, when more than one channel
is used for filtering one signal (one carrier).
CRCF Coefficient Offset <5:0>
This register is used to specify which section of the 64-word
coefficient memory is used for a filter. It can be used to select
between multiple filters that are loaded into memory and
referenced by this pointer. This register is shadowed, and the
filter pointer is updated every time a new filter is started. This
allows the coefficient offset to be written even while a filter is
being computed without disturbing operation. The next sample
comes out of the CRCF with the new filter.
CRCF Taps <6:0>
This register is written with one less than the number of taps
that are calculated by the CRCF filter. The filter length is given
by the decimal value of this register plus 1. A value of 0 repre-
sents a 1-tap filter, and a value of 0x28 (40 decimal) represents a
41-tap filter.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全称:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-125EBZ | 功能描述:BOARD EVAL W/AD6655 & SOFTWARE RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
| AD6655-125EBZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-150EBZ | 功能描述:BOARD EVAL FOR 150MSPS AD6655 RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
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