参数资料
型号: AD6654CBCZ
厂商: Analog Devices Inc
文件页数: 51/88页
文件大小: 0K
描述: IC ADC 14BIT W/4CH RSP 256CSPBGA
标准包装: 1
位数: 14
采样率(每秒): 92.16M
数据接口: 串行,并联
转换器数目: 1
功率耗散(最大): 2.5W
电压电源: 模拟和数字
工作温度: -25°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 256-BGA,CSPBGA
供应商设备封装: 256-CSPBGA(17x17)
包装: 托盘
输入数目和类型: 1 个差分,单极
AD6654
Rev. 0 | Page 55 of 88
MASTER/SLAVE PCLK MODES
The parallel ports can operate in either master or slave mode.
The mode is set via PCLK master mode bit in the Parallel Port
Control 2 register. The parallel ports power up in slave mode to
avoid possible contentions on the PCLK pin.
In master mode, PCLK is an output derived by dividing
PLL_CLK down by the PCLK divisor. The PCLK divisor can
have a value of 1, 2, 4, or 8, depending on the 2-bit PCLK
divisor word setting in the Parallel Port Control 2 register. The
highest PLCK rate in master mode is 200 MHz. Master mode is
selected by setting the PCLK master mode bit in the Parallel
Port Control 2 register.
divisor
PCLK
rate
CLK
PLL
rate
PCLK
_
=
In slave mode, external circuitry provides the PCLK signal.
Slave mode PCLK signals can be either synchronous or
asynchronous. The maximum slave mode PCLK frequency is
also 200 MHz.
PCLK
tDPREQ
PxREQ
PxACK
tDPP
Px [15:0]
I [15:8]
Q [15:8]
PxIQ
tDPIQ
PxCH [2:0]
PxCH [2:0] = CHANNEL #
tDPCH
0000 +
GAIN [11:0]
PxGAIN
tDPGAIN
05156-049
Figure 60. Parallel I/Q Mode with an AGC Gain Word
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