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参数资料
| 型号： | AD6654CBCZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 45/88页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT W/4CH RSP 256CSPBGA |
| 标准包装： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 92.16M |
| 数据接口： | 串行，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5W |
| 电压电源： | 模拟和数字 |
| 工作温度： | -25°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BGA，CSPBGA |
| 供应商设备封装： | 256-CSPBGA（17x17） |
| 包装： | 托盘 |
| 输入数目和类型： | 1 个差分，单极 |
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AD6654
Rev. 0 | Page 5 of 88
can perform. It can also allow complex filtering operations to be
achieved in the programmable filters.
The digital AGC provides the user with scaled digital outputs
based on the rms level of the signal present at the output of the
digital filters. The user can set the requested level and time
constant of the AGC loop for optimum performance of the
postprocessor. This is a critical function in the base station for
CDMA application, where the power level must be well
controlled going into the RAKE receivers. It has programmable
clipping and rounding control to provide different output
resolutions.
The overall filter response for the AD6654 is the composite of
all the combined filter stages. Each successive filter stage is
capable of narrower transition bandwidths, but requires a
greater number of CLK cycles to calculate the output. The
AD6654 features a fractional clock multiplier that uses the ADC
clock (which is slower than the DDC’s processing speed) to
produce a DDC master clock up to 200 MHz. This feature
allows fractional multiplication of the input clock to allow the
DDC to function at maximum speed while maintaining edge
identity to the ADC clock.
More decimation in the first filter stage minimizes overall
power consumption. Data from the device is interfaced to a
DSP/FPGA/baseband processor via high speed parallel ports
(preferred), or a DSP-compatible microprocessor interface.
The AD6654 is available in 4-channel and 6-channel versions.
The primary focus of the data sheet is on the 6-channel part.
The only difference between the 6-channel and 4-channel
devices is that, on the 4-channel version, Channel 4 and
Channel 5 are not available (see Figure 1). The 4-channel device
has the same DDC input port features, output ports, and
memory map as the 6-channel device. On the 4-channel
version, the memory map section for Channel 4 and Channel 5
can be programmed and read back, but the two extra channels
are disabled internally.
PRODUCT HIGHLIGHTS
1.
Integrated 14-bit, 92.16 MSPS ADC.
2.
Track-and-hold amplifier analog input for excellent IF
sampling up to 200 MHz.
3.
Four or six independent digital filtering channels.
4.
RMS/peak power monitoring of the ADC data port and
96 dB range AGCs before the output ports.
5.
Three programmable RAM coefficient filters, three half-
band filters, two fixed coefficient filters, and one fifth-
order CIC filter per channel.
6.
Complex filtering by combining filtering capability of
multiple channels.
7.
Three 16-bit parallel output ports operating at up to
200 MHz clock.
8.
Blackfin- and TigerSHARC-compatible, 8-/16-bit
microprocessor port.
9.
Synchronous serial communications port is compatible
with most serial interface standards: SPORT, SPI, and SSR.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6654XBCZ | 制造商:Analog Devices 功能描述:14-BIT, 92.16 MSPS, 4 & 6-CHANNEL WIDEBAND IF TO BASE BAND R - Bulk |
| AD6655 | 制造商:AD 制造商全称:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-125EBZ | 功能描述:BOARD EVAL W/AD6655 & SOFTWARE RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
| AD6655-125EBZ1 | 制造商:AD 制造商全称:Analog Devices 功能描述:IF Diversity Receiver |
| AD6655-150EBZ | 功能描述:BOARD EVAL FOR 150MSPS AD6655 RoHS:是 类别:RF/IF 和 RFID >> RF 评估和开发套件，板 系列:- 标准包装:1 系列:- 类型:GPS 接收器 频率:1575MHz 适用于相关产品:- 已供物品:模块 其它名称:SER3796 |
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