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参数资料
型号： AD6654CBCZ
厂商： Analog Devices Inc
文件页数： 71/88页
文件大小： 0K
描述： IC ADC 14BIT W/4CH RSP 256CSPBGA
标准包装： 1
位数： 14
采样率（每秒）： 92.16M
数据接口： 串行，并联
转换器数目： 1
功率耗散（最大）： 2.5W
电压电源： 模拟和数字
工作温度： -25°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 256-BGA，CSPBGA
供应商设备封装： 256-CSPBGA（17x17）
包装： 托盘
输入数目和类型： 1 个差分，单极
AD6654
Rev. 0 | Page 73 of 88
Table 28. Memory Map
8-Bit Hex
Address
Byte 3
Byte 2
Byte 1
Byte 0
8-Bit Hex
Address
0x03
Open <7:6>, Channel
Enable <5:0>
Open <7:6>, Channel I/O
Access Control <5:0>
Chip I/O Access Control
<7:0> (default 0x00)
Open <7:0>
0x00
0x07
Open <15:11>, Reserved <10:0> (default 0x06FC)
Soft Synchronization
Configuration <7:0>
Pin Synchronization
Configuration <7:0>
0x04
0x0B
Interrupt Mask <15:0>
Interrupt Status <15:0> (read only, default 0x00)
0x08
ADC Input Port Register Map— Addresses 0x0C to 0x57
0x0F
ADC Input Control <31:0>
0x0C
0x13
Open <15:0>
ADC CLK Control <15:0> (default 0x0000)
0x10
0x4B
ADC Gain Control <7:0>
Open <23:20>, ADC Dwell Timer <19:0>
0x48
0x4F
Open <7:0>
ADC Power Monitor Period <23:0>
0x4C
0x53
Open <7:5>, ADC Signal
Monitor <4:0>
ADC Power Monitor Output <23:0>
0x50
0x57
Open <15:10>, ADC Lower Threshold <9:0>
Open <15:10>, ADC Upper Threshold <9:0>
0x54
Channel Register Map—Addresses 0x68 to 0xBB
0x6B
Open <15:0>
Open <15:9>, NCO Control <8:0>
0x68
0x6F
NCO Start Hold-Off Counter <15:0>
NCO Frequency Hold-Off Counter <15:0>
0x6C
0x73
NCO Frequency <31:0> (default 0x0000 0000)
0x70
0x77
Open <15:0>
NCO Phase Offset <15:0> (default 0x0000)
0x74
0x7B
Open <7:1>, CIC Bypass <0>
Open <7:5>, CIC
Decimation <4:0>
Open <7:5>, CIC Scale
Factor <4:0>
Open <7:4>, FIR-HB
Control <3:0>
0x78
0x7F
Open <15:0>
Open <15:13>, MRCF Control <12:0>
0x7C
0x83
Open <7:6>, MRCF
Coefficient 3 <5:0>
Open <7:6>, MRCF
Coefficient 2 <5:0>
Open <7:6>, MRCF
Coefficient 1 <5:0>
Open <7:6>, MRCF
Coefficient 0 <5:0>
0x80
0x87
Open <7:6>, MRCF
Coefficient 7 <5:0>
Open <7:6>, MRCF
Coefficient 6 <5:0>
Open <7:6>, MRCF
Coefficient 5 <5:0>
Open <7:6>, MRCF
Coefficient 4 <5:0>
0x84
0x8B
Open <15:13>, DRCF Control Register <12:0>
Open <7:6>, DRCF
Coefficient Offset <5:0>
Open <7>, DRCF Taps
<6:0>
0x88
0x8F
Open <15:0>
Open <7:6>, DRCF Final
Address <5:0>
Open <7:6>, DRCF Start
Address <5:0>
0x8C
0x93
Open<15:0>
Open<15:14>, DRCF Coefficient Memory <13:0>
0x90
0x97
Open <15:13>, CRCF Control Register <12:0>
Open <7:6>, CRCF
Coefficient Offset <5:0>
Open <7>, CRCF Taps
<6:0>
0x94
0x9B
Open <15:0>
Open <7:6>, CRCF Final
Address <5:0>
Open <7:6>, CRCF Start
Address <5:0>
0x98
0x9F
Open <7:0>
Open <23:20>, CRCF Coefficient Memory <19:0>
0x9C
0xA3
Open <15:11>, AGC Control Register <10:0>
AGC Hold-Off Register <15:0>
0xA0
0xA7
Open <15:12>, AGC Update Decimation <11:0>
Open <15:12>, AGC Signal Gain <11:0>
0xA4
0xAB
Open <15:12>, AGC Error Threshold <11:0>
Open <7:6>, AGC Average
Samples <5:0>
AGC Pole Location <7:0>
0xA8
0xAF
Open <7:0>
AGC Desired Level <7:0>
AGC Loop Gain2 <7:0>
AGC Loop Gain1 <7:0>
0xAC
0xB3
Open <7:0>
BIST I Path Signature Register <23:0> (read only)
0xB0
0xB7
Open <7:0>
BIST Q Path Signature Register <23:0> (read only)
0xB4
0xBB
Open <15:0>
BIST Control <15:0>
0xB8
Output Port Register Map—Addresses 0xBC to 0xE7
0xBF
Open <7:0>
Parallel Port Output Control <23:0>
0xBC
0xC3
Open <15:0>
Open <15:10>, Output Port Control <9:0>
0xC0
0xC7
AGC0, I Output <15:0> (read only)
AGC0, Q Output <15:0> (read only)
0xC4
0xCB
AGC1, I Output <15:0> (read only)
AGC1, Q Output <15:0> (read only)
0xC8
0xCF
AGC2, I Output <15:0> (read only)
AGC2, Q Output <15:0> (read only)
0xCC
0xD3
AGC3, I Output <15:0> (read only)
AGC3, Q Output <15:0> (read only)
0xD0
0xD7
AGC4, I Output <15:0> (read only)
AGC4, Q Output <15:0> (read only)
0xD4
0xDB
AGC5, I Output <15:0> (read only)
AGC5, Q Output <15:0> (read only)
0xD8
0xDF
Open <15:12>, AGC0 RSSI Output <11:0> (read only)
Open <15:12>, AGC1 RSSI Output <11:0> (read only)
0xDC
0xE3
Open <15:12>, AGC2 RSSI Output <11:0> (read only)
Open <15:12>, AGC3 RSSI Output <11:0> (read only)
0xE0
0xE7
Open <15:12>, AGC4 RSSI Output <11:0> (read only)
Open <15:12>, AGC5 RSSI Output <11:0> (read only)
0xE4
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